|
Bus Slots and I/O Cards
At the heart of every system is the motherboard; we discussed the various motherboards in Chapter 4 - Motherboards. A motherboard
is made up of components. The major component that determines how the motherboard actually works is called the bus. In this
chapter, system buses are discussed.
What Is a Bus?
A bus is nothing but a common pathway across which data can travel within a computer. This pathway is used for communication
and can be established between two or more computer elements. A PC has many kinds of buses, including the following:
- Processor bus
- Address bus
- I/O bus
- Memory bus
If you hear someone talking about the bus in a PC, chances are good that he or she is referring to the I/O bus,
which also is called the expansion slot bus. Whatever name it goes by, this bus is the main system bus and the one
over which most data flows. The I/O bus is the highway for most data in your system. Anything that goes to or from any device--including
your video system, disk drives, and printer--travels over this bus. The busiest I/O pathway typically is to and from your
video card.
Because the I/O bus is the primary bus in your computer system, it is the main focus of discussion in this chapter. The
other buses deserve some attention, however, and they are covered in the following sections.
The Processor Bus
The processor bus is the communication pathway between the CPU and immediate support chips. These support chips
are usually called the chipset in modern systems. This bus is used to transfer data between the CPU and the main system
bus, for example, or between the CPU and an external memory cache. Figure 5.1 shows how this bus fits into a typical PC system.
FIG. 5.1 The processor bus.
Because the purpose of the processor bus is to get information to and from the CPU at the fastest possible speed, this
bus operates at a much faster rate than any other bus in your system; no bottleneck exists here. The bus consists of electrical
circuits for data, for addresses (the address bus, which is discussed in the following section), and for control purposes.
In a Pentium-based system, the processor bus has 64 data lines, 32 address lines, and associated control lines. The Pentium
Pro and Pentium II have 36 address lines, but otherwise are the same as the Pentium and Pentium MMX.
The processor bus operates at the same base clock rate as the CPU does externally. This can be misleading as most CPUs
these days run internally at a higher clock rate than they do externally. For example, a Pentium 100 system has a Pentium
CPU running at 100MHz internally, but only 66MHz externally. A Pentium 133, Pentium 166, and even a Pentium Pro 200 also run
the processor external bus at 66MHz. In most newer systems, the actual processor speed is some multiple (1.5x, 2x, 2.5x, 3x,
and so on) of the processor bus. For more information on this, see "Processor Speed Ratings" in Chapter 6 - The Microprocessor.
The processor bus is tied to the external processor pin connections and can transfer one bit of data per data line every
one or two clock cycles. Thus, a Pentium, Pentium Pro, or Pentium II can transfer 64 bits of data at a time.
To determine the transfer rate for the processor bus, you multiply the data width (64 bits for a Pentium, Pentium Pro,
or Pentium II) by the clock speed of the bus (the same as the base or unmultiplied clock speed of the CPU). If you are using
a Pentium, Pentium MMX, Pentium Pro, or Pentium II chip that runs at a 66MHz motherboard speed, and it can transfer a bit
of data each clock cycle on each data line, you have a maximum instantaneous transfer rate of 528M/sec. You get this result
by using the following formula: 66MHz x 64 bits = 4,224Mbit/sec 4,224Mbit/sec ÷ 8 = 528M/sec This transfer rate, often called
the bandwidth of the bus, represents a maximum. Like all maximums, this rate does not represent the normal operating
bandwidth; you should expect much lower average throughput. Other limiting factors such as chipset design, memory design and
speed, and so on, conspire to lower the effective average throughput.
The Memory Bus
The memory bus is used to transfer information between the CPU and main memory--the RAM in your system. This bus
is either a part of the processor bus itself, or in most cases is implemented separately by a dedicated chipset that is responsible
for transferring information between the processor bus and the memory bus. Systems that run at mother-board clock speeds of
16MHz or faster cycle at rates that exceed the capabilities of standard Dynamic RAM chips. In virtually all systems that are
16MHz or faster, there will be a special memory controller chipset that controls the interface between the faster processor
bus and the slower main memory. This chipset typically is the same chipset that is responsible for managing the I/O bus. Figure
5.2 shows how the memory bus fits into your PC.
FIG. 5.2 The memory bus.
The information that travels over the memory bus is transferred at a much slower rate than the information on the processor
bus. The chip sockets or the slots for memory SIMMs/DIMMs (Dual Inline Memory Modules) are connected to the memory bus in
much the same way that expansion slots are connected to the I/O bus.
CAUTION: Notice that the main memory bus is always the same width as the processor bus.
This means that in a 64-bit system, such as the various Pentium CPUs, you will have a 64-bit memory bus. This will define
the size of what is called a "bank" of memory. For example, a 486DX4 processor has a 32-bit bus, so the memory in that system
must be added 32 bits at a time for each bank. If you are using 30-pin (8-bit) SIMMs, then four will be required per bank;
if the system uses 72-pin (32-bit) SIMMs, then only one has to be added at a time to make up a bank. Pentium systems are 64-bit
and always require two 72-pin (32 bits each) SIMMs to be added at a time. Newer systems use 168-pin DIMMs, which are 64 bits
each. These compose a single bank in a 64-bit system.
The Address Bus
The address bus actually is a subset of the processor and memory buses. In our discussion of the processor bus,
you learned that a Pentium system bus consists of 64 data lines, 32 address lines (36 in a Pentium Pro or Pentium II), and
a few control lines. These address lines constitute the address bus; in most block diagrams, this bus is actually considered
a part of the processor and memory buses.
The address bus is used to indicate what address in memory or what address on the system bus are to be used in a data transfer
operation. The address bus indicates precisely where the next bus transfer or memory transfer will occur. The size of the
memory bus also controls the amount of memory that the CPU can address directly.
The Need for Expansion Slots
The I/O bus or expansion slots are what enables your CPU to communicate with peripheral devices. The bus and its associated
expansion slots are needed because basic systems cannot possibly satisfy all the needs of all the people who buy them. The
I/O bus enables you to add devices to your computer to expand its capabilities. The most basic computer components, such as
sound cards and video cards, can be plugged into expansion slots; you also can plug in more specialized devices, such as network
interface cards, SCSI host adapters, and others.
NOTE: In most PC systems, a variety of basic peripheral devices are directly built into
the motherboard, like primary and secondary IDE controllers, a floppy controller, serial ports, and a parallel port. This
is normally contained on a single chip called a Super I/O chip. Many will even add more items such as an integrated mouse
port, video adapter, SCSI host adapter, or network interface also built into the motherboard; in such a system, an expansion
slot on the I/O bus is probably not even needed. Nevertheless, these built-in controllers and ports still use the I/O bus
to communicate with the CPU. In essence, even though they are built in, they act as if they are cards plugged into the system's
bus slots.
Although some PC systems provide only a single expansion slot, most provide up to eight slots on the motherboard. This
slot typically is called a riser card slot. The riser card that plugs into it in turn has expansion slots on its sides.
Standard adapter cards are installed in the riser card, meaning that the adapter cards end up being parallel to the motherboard
rather than perpendicular to it.
Riser cards are used when a vendor wants to produce a computer that is shorter in height than normal. These computers usually
are called Slimline, Low Profile, or sometimes even pizza-box systems. Even though this type of configuration
may seem to be odd, the actual bus used in these systems is the same kind used in normal computer systems; the only difference
is the use of the riser card.
Bus Mastering
Newer bus types use a technology called bus mastering to speed up the system. In essence, a bus master is
an adapter with its own processor that can execute operations independently of the CPU. To work properly, bus-mastering technology
relies on an arbitration unit, most often called an integrated system peripheral (ISP) chip. The ISP enables a bus-mastered
board to temporarily take exclusive control of the system, as though the board were the entire system. Because the board has
exclusive control of the system, it can perform operations very quickly. A bus-mastering hard drive controller, for example,
achieves much greater data throughput with a fast drive than can controller cards that are not bus-mastered.
The ISP determines which device gains control by using a four-level order of priority:
- System-memory refresh
- The CPU itself
- Bus masters
- DMA transfers
A bus-mastering adapter board notifies the ISP when it wants control of the system. At the earliest possible time (after
the higher priorities have been satisfied), the ISP hands control over to the bus-mastered board. The board, in turn, has
built-in circuitry to keep it from taking over the system for periods of time that would interfere with first-priority operations,
such as memory refresh.
I/O Buses
Since the introduction of the first PC, many I/O buses have been introduced. The reason is quite simple: Faster I/O speeds
are necessary for better system performance. This need for higher performance involves three main areas:
- Faster CPUs
- Increasing software demands
- Greater multimedia requirements
Each of these areas requires the I/O bus to be as fast as possible. Surprisingly, most 486 and Pentium PC systems still
had the same basic bus architecture as the 1984 vintage IBM PC/AT. However, they also include a second high-speed local I/O
bus such as VL-Bus or PCI, which offer much greater performance for adapters that need it.
One of the primary reasons why new I/O-bus structures have been slow in coming is compatibility--that old Catch-22 that
anchors much of the PC industry to the past. One of the hallmarks of the PC's success is its standardization. This standardization
spawned thousands of third-party I/O cards, each originally built for the early bus specifications of the PC. If a new high-performance
bus system is introduced, it often has to be compatible with the older bus systems so that the older I/O cards do not become
obsolete. Therefore, bus technologies seem to evolve rather than make quantum leaps forward.
You can identify different types of I/O buses by their architecture. The main types of I/O architecture are:
- The ISA Bus
- The Micro Channel Bus (MCA)
- The EISA Bus
- The PC Card Bus (PCMCIA)
NOTE: The newer types of buses are described in the "Local Buses" section, later in this
chapter.
The differences among these buses consist primarily of the amount of data that they can transfer at one time and the speed
at which they can do it. Each bus architecture is implemented by a chipset that is connected to the processor bus. Typically,
this chipset also controls the memory bus (refer to Figure 5.2). The following sections describe the different types of PC
buses.
The ISA Bus
ISA, which is an acronym for Industry Standard Architecture, is the bus architecture that was introduced
as an 8-bit bus with the original IBM PC in 1981 and later expanded to 16 bits with the IBM PC/AT in 1984. For many years,
ISA has been the primary architecture used in most computer systems. It may seem amazing that such a seemingly antiquated
architecture was used for such a long time, but this is true for reasons of reliability, affordability, and compatibility,
plus this old bus was still faster than many of the peripherals that we connected to it!
Two versions of the ISA bus exist, based on the number of data bits that can be transferred on the bus at a time. The older
version is an 8-bit bus; the newer version is a 16-bit bus. The original 8-bit version ran at 4.77MHz in the PC and XT. The
16-bit version used in the AT ran at 6MHz and then 8MHz. Later, the industry as a whole agreed on an 8.33MHz maximum standard
speed for 8- and 16-bit versions of the ISA bus for backward compatibility. Some systems have the ability to run the ISA bus
faster than this, but some adapter cards will not function properly at higher speeds. ISA data transfers require anywhere
from two to eight cycles. Therefore, the theoretical maximum data rate of the ISA bus is about 8M/sec, as the following formula
shows:
8MHz x 16 bits = 128Mbit/sec 128Mbit/sec ÷ 2 cycles = 64Mbit/sec 64Mbit/sec ÷ 8 = 8M/sec
The bandwidth of the 8-bit bus would be half this figure (4M/sec). Remember, however, that these figures are theoretical
maximums; because of I/O bus protocols, the effective bandwidth is much lower--typically by almost half.
The 8-Bit ISA Bus
This bus architecture is used in the original IBM PC computers. Physically, the 8-bit ISA expansion slot resembles the
tongue-and-groove system that furniture makers once used to hold two pieces of wood together. It is specifically called a
Card/Edge connector. An adapter card with 62 contacts on its bottom edge plugs into a slot on the motherboard that
has 62 matching contacts. Electronically, this slot provides eight data lines and 20 addressing lines, enabling the slot to
handle 1M of memory.
Table 5.1 describes the pinouts for the 8-bit ISA bus.
Table 5.1 Pinouts for the 8-bit ISA Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
Ground |
A1 |
-I/O CH CHK |
B2 |
RESET DRV |
A2 |
Data 7 |
B3 |
+5v |
A3 |
Data 6 |
B4 |
IRQ 2 |
A4 |
Data 5 |
B5 |
-5v |
A5 |
Data 4 |
B6 |
DRQ 2 |
A6 |
Data 3 |
B7 |
-12v |
A7 |
Data 2 |
B8 |
-CARD SLCTD |
A8 |
Data 1 |
B9 |
+12v |
A9 |
Data 0 |
B10 |
Ground |
A10 |
-I/O CH RDY |
B11 |
-SMEMW |
A11 |
AEN |
B12 |
-SMEMR |
A12 |
Address 19 |
B13 |
-IOW |
A13 |
Address 18 |
B14 |
-IOR |
A14 |
Address 17 |
B15 |
-DACK 3 |
A15 |
Address 16 |
B16 |
DRQ 3 |
A16 |
Address 15 |
B17 |
-DACK 1 |
A17 |
Address 14 |
B18 |
DRQ 1 |
A18 |
Address 13 |
B19 |
-REFRESH |
A19 |
Address 12 |
B20 |
CLK (4.77MHz) |
A20 |
Address 11 |
B21 |
IRQ 7 |
A21 |
Address 10 |
B22 |
IRQ 6 |
A22 |
Address 9 |
B23 |
IRQ 5 |
A23 |
Address 8 |
B24 |
IRQ 4 |
A24 |
Address 7 |
B25 |
IRQ 3 |
A25 |
Address 6 |
B26 |
-DACK 2 |
A26 |
Address 5 |
B27 |
T/C |
A27 |
Address 4 |
B28 |
BALE |
A28 |
Address 3 |
B29 |
+5v |
A29 |
Address 2 |
B30 |
OSC (14.3MHz) |
A30 |
Address 1 |
B31 |
Ground |
A31 |
Address 0 |
A = Component side, B = Back side
Figure 5.3 shows how these pins are oriented in the expansion slot.
FIG. 5.3 The 8-bit ISA bus connector.
Although the design of the bus is simple, IBM waited until 1987 to publish full specifications for the timings of the data
and address lines, so in the early days of PC compatibles, manufacturers had to do their best to figure out how to make adapter
boards. This problem was solved, however, as PC-compatible personal computers became more widely accepted as the industry
standard and manufacturers had more time and incentive to build adapter boards that worked correctly with the bus.
The dimensions of 8-bit ISA adapter cards are as follows:
4.2 inches (106.68mm) high 13.13 inches (333.5mm) long 0.5 inch (12.7mm) wide
The 16-Bit ISA Bus
IBM threw a bombshell on the PC world when it introduced the AT with the 286 processor in 1984. This processor had a 16-bit
data bus, which meant that communications between the processor and the motherboard as well as memory would now be 16 bits
wide instead of only 8 bits wide.
Although this processor could have been installed on a motherboard with only an 8-bit I/O bus, that would have meant a
huge sacrifice in the performance of any adapter cards or other devices installed on the bus. The introduction of the 286
chip posed a problem for IBM in relation to its next generation of PCs. Should the company create a new I/O bus and associated
expansion slots, or should it try to come up with a system that could support both 8- and 16-bit cards? IBM opted for the
latter solution, and the PC/AT was introduced with a set of expansion slots with 16-bit extension connectors. You can plug
an 8-bit card into the forward part of the slot or a 16-bit card into both parts of the slot.
NOTE: The expansion slots for the 16-bit ISA bus also introduced access keys to the PC environment.
An access key is a cutout or notch in an adapter card that fits over a corresponding tab in the connector into which the adapter
card is inserted. Access keys typically are used to keep adapter cards from being inserted into a connector improperly.
The extension connector in each 16-bit expansion slot adds 36 connector pins to carry the extra signals necessary to implement
the wider data path. In addition, two of the pins in the 8-bit portion of the connector were changed. These two minor changes
do not alter the function of 8-bit cards.
Table 5.2 describes the pinouts for the full 16-bit ISA expansion slot.
Table 5.2 Pinouts for the 16-bit ISA Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
Ground |
A1 |
-I/O CH CHK |
B2 |
RESET DRV |
A2 |
Data 7 |
B3 |
+5v |
A3 |
Data 6 |
B4 |
IRQ 9 |
A4 |
Data 5 |
B5 |
-5v |
A5 |
Data 4 |
B6 |
DRQ 2 |
A6 |
Data 3 |
B7 |
-12v |
A7 |
Data 2 |
B8 |
-0 WAIT |
A8 |
Data 1 |
B9 |
+12v |
A9 |
Data 0 |
B10 |
Ground |
A10 |
-I/O CH RDY |
B11 |
-SMEMW |
A11 |
AEN |
B12 |
-SMEMR |
A12 |
Address 19 |
B13 |
-IOW |
A13 |
Address 18 |
B14 |
-IOR |
A14 |
Address 17 |
B15 |
-DACK 3 |
A15 |
Address 16 |
B16 |
DRQ 3 |
A16 |
Address 15 |
B17 |
-DACK 1 |
A17 |
Address 14 |
B18 |
DRQ 1 |
A18 |
Address 13 |
B19 |
-REFRESH |
A19 |
Address 12 |
B20 |
CLK (8.33MHz) |
A20 |
Address 11 |
B21 |
IRQ 7 |
A21 |
Address 10 |
B22 |
IRQ 6 |
A22 |
Address 9 |
B23 |
IRQ 5 |
A23 |
Address 8 |
B24 |
IRQ 4 |
A24 |
Address 7 |
B25 |
IRQ 3 |
A25 |
Address 6 |
B26 |
-DACK 2 |
A26 |
Address 5 |
B27 |
T/C |
A27 |
Address 4 |
B28 |
BALE |
A28 |
Address 3 |
B29 |
+5v |
A29 |
Address 2 |
B30 |
OSC (14.3MHz) |
A30 |
Address 1 |
B31 |
Ground |
A31 |
Address 0 |
|
Access key |
|
Access key |
D1 |
-MEM CS16 |
C1 |
-SBHE |
D2 |
-I/O CS16 |
C2 |
Latch address 23 |
D3 |
IRQ 10 |
C3 |
Latch address 22 |
D4 |
IRQ 11 |
C4 |
Latch address 21 |
D5 |
IRQ 12 |
C5 |
Latch address 20 |
D6 |
IRQ 15 |
C6 |
Latch address 19 |
D7 |
IRQ 14 |
C7 |
Latch address 18 |
D8 |
-DACK 0 |
C8 |
Latch address 17 |
D9 |
DRQ 0 |
C9 |
-MEMR |
D10 |
-DACK 5 |
C10 |
-MEMW |
D11 |
DRQ 5 |
C11 |
Data 8 |
D12 |
-DACK 6 |
C12 |
Data 9 |
D13 |
DRQ 6 |
C13 |
Data 10 |
D14 |
-DACK 7 |
C14 |
Data 11 |
D15 |
DRQ 7 |
C15 |
Data 12 |
D16 |
+5v |
C16 |
Data 13 |
D17 |
-MASTER |
C17 |
Data 14 |
D18 |
Ground |
C18 |
Data 15 |
A/C = Component side, B/D = Back side
Figure 5.4 shows how these pins are oriented in the expansion slot.
FIG. 5.4 The 16-bit ISA bus connector.
The extended 16-bit slots physically interfere with some 8-bit adapter cards that have a skirt--an extended area
of the card that drops down toward the motherboard just after the connector. To handle these cards, IBM left two expansion
ports in the PC/AT without the 16-bit extensions. These slots, which are identical to the expansion slots in earlier systems,
can handle any skirted PC or XT expansion card.
NOTE: 16-bit ISA expansion slots were introduced in 1984. Since then, virtually every manufacturer
of 8-bit expansion cards have designed them without drop-down skirts so that they fit properly in 16-bit slots. Most 16-bit
systems do not have any 8-bit only slots, because a properly designed 8-bit card will work in any 16-bit slot.
The dimensions of a typical AT expansion board are as follows:
4.8 inches (121.92mm) high 13.13 inches (333.5mm) long 0.5 inch (12.7mm) wide
Two heights actually are available for cards that are commonly used in AT systems: 4.8 inches and 4.2 inches (the height
of older PC-XT cards). The shorter cards became an issue when IBM introduced the XT Model 286. Because this model has an AT
motherboard in an XT case, it needs AT-type boards with the 4.2-inch maximum height. Most board makers trimmed the height
of their boards; many manufacturers now make only 4.2-inch tall (or less) boards so that they will work in systems with either
profile.
Plug and Play ISA
In 1993, Intel and Microsoft developed a Plug and Play ISA bus (PnP ISA), that allowed the computer to automatically detect
en setup ISA peripherals. PnP ISA cards can communicate with the system BIOS and the operating system to convey information
about what system resources are needed. The BIOS and operating system, in turn, resolve conflicts (wherever possible) and
inform the adapter cards which specific resources it should use. The adapter card then can modify its configuration to use
the specified resources. This means that the BIOS also has to be PnP-compatible. In fact, Plug and Play first became popular
in 1996, with the introduction of Windows 95.
NOTE: Refer to the "Plug and Play Systems" section later in this chapter for more information
about Plug and Play hardware and software.
32-Bit ISA-Based Buses
After 32-bit CPUs became available, it was some time before 32-bit bus standards became available. Before MCA and EISA
specs were released, some vendors began creating their own proprietary 32-bit buses, which were extensions of the ISA bus.
Although the proprietary buses were few and far between, they do exist. The expanded portions of the bus typically are used
for proprietary memory expansion or video cards. Because the systems are proprietary (meaning that they are nonstandard),
pinouts and specifications are not available.
The Micro Channel Bus
The introduction of 32-bit chips meant that the ISA bus could not handle the power of another new generation of CPUs. The
386DX chips can transfer 32 bits of data at a time, but the ISA bus can handle a maximum of 16 bits. Rather than extend the
ISA bus again, IBM decided to build a new bus with a new connector; the result was the MCA bus. MCA (an acronym for
Micro Channel Architecture) is completely different from the ISA bus and is technically superior in every way.
IBM not only wanted to replace the old ISA standard but also to receive royalties on it; the company required vendors that
licensed the new MCA bus to pay IBM royalties for using the ISA bus in all previous systems. This requirement led to the development
of the competing EISA bus (see the next section on the EISA Bus) and hindered acceptance of the MCA bus. Another reason why
MCA has not been adopted universally for systems with 32-bit slots is that adapter cards designed for ISA systems do not work
in MCA systems.
NOTE: The MCA bus is not compatible with the older ISA bus, so cards designed for the ISA
bus do not work in an MCA system.
MCA runs asynchronously with the main processor, meaning that fewer possibilities exist for timing problems among adapter
cards plugged into the bus.
MCA systems produced a new level of ease of use, as anyone who has set up one of these systems can tell you. An MCA system
has no jumpers and switches--neither on the motherboard nor on any expansion adapter. You don't need an electrical engineering
degree to plug a card into a PC.
The MCA bus also supports bus mastering. Through implementing bus mastering, the MCA bus provides significant performance
improvements over the older ISA buses. (Bus mastering is also implemented in the EISA bus.) In the MCA bus mastering implementation,
any bus mastering devices can request unobstructed use of the bus in order to communicate with another device on the bus.
The request is made through a device known as the Central Arbitration Control Point (CACP). This device arbitrates
the competition for the bus, making sure all devices have access and that no single device monopolizes the bus.
Each device is given a priority code to ensure that order is preserved within the system. The main CPU is given the lowest
priority code. Memory refresh has the highest priority, followed by the DMA channels, and then the bus masters installed in
the I/O slots. One exception to this is when an NMI (non-maskable interrupt) occurs. In this instance, control returns to
the CPU immediately.
The MCA specification provides for four adapter sizes, which are described in Table 5.3.
Table 5.3 Physical Sizes of MCA Adapter Cards
Adapter Type |
Height (in Inches) |
Length (in Inches) |
Type 3 |
3.475 |
12.3 |
Type 3 half |
3.475 |
6.35 |
Type 5 |
4.825 |
13.1 |
Type 9 |
9.0 |
13.1 |
Four types of slots are involved in the MCA design:
- 16-bit
- 16-bit with video extensions
- 16-bit with memory-matched extensions
- 32-bit
Table 5.4 describes the pinouts for the MCA connector.
Table 5.4 Pinouts for the MCA Connector
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
Audio Ground |
A1 |
-CD SETUP |
B2 |
Audio |
A2 |
MADE 24 |
B3 |
Ground |
A3 |
Ground |
B4 |
OSC (14.3MHz) |
A4 |
Address 11 |
B5 |
Ground |
A5 |
Address 10 |
B6 |
Address 23 |
A6 |
Address 9 |
B7 |
Address 22 |
A7 |
+5v |
B8 |
Address 21 |
A8 |
Address 8 |
B9 |
Ground |
A9 |
Address 7 |
B10 |
Address 20 |
A10 |
Address 6 |
B11 |
Address 19 |
A11 |
+5v |
B12 |
Address 18 |
A12 |
Address 5 |
B13 |
Ground |
A13 |
Address 4 |
B14 |
Address 17 |
A14 |
Address 3 |
B15 |
Address 16 |
A15 |
+5v |
B16 |
Address 15 |
A16 |
Address 2 |
B17 |
Ground |
A17 |
Address 1 |
B18 |
Address 14 |
A18 |
Address 0 |
B19 |
Address 13 |
A19 |
+12v |
B20 |
Address 12 |
A20 |
-ADL |
B21 |
Ground |
A21 |
-PREEMPT |
B22 |
-IRQ 9 (2) |
A22 |
-BURST |
B23 |
-IRQ 3 |
A23 |
-12v |
B24 |
-IRQ 4 |
A24 |
ARB 0 |
B25 |
Ground |
A25 |
ARB 1 |
B26 |
-IRQ 5 |
A26 |
ARB 2 |
B27 |
-IRQ 6 |
A27 |
-12v |
B28 |
-IRQ 7 |
A28 |
ARB 3 |
B29 |
Ground |
A29 |
ARB/-GNT |
B30 |
-DPAREN |
A30 |
-TC |
B31 |
DPAR 0 |
A31 |
+5v |
B32 |
-CHCK |
A32 |
-S0 |
B33 |
Ground |
A33 |
-S1 |
B34 |
-CMD |
A34 |
M/-IO |
B35 |
CHRDYRTN |
A35 |
+12v |
B36 |
-CD SFDBK |
A36 |
CD CHRDY |
B37 |
Ground |
A37 |
Data 0 |
B38 |
Data 1 |
A38 |
Data 2 |
B39 |
Data 3 |
A39 |
+5v |
B40 |
Data 4 |
A40 |
Data 5 |
B41 |
Ground |
A41 |
Data 6 |
B42 |
CHRESET |
A42 |
Data 7 |
B43 |
-SD STROBE |
A43 |
Ground |
B44 |
-SDR 0 |
A44 |
-DS 16 RTN |
B45 |
Ground |
A45 |
-REFRESH |
B46 |
Access key |
A46 |
Access key |
B47 |
Access key |
A47 |
Access key |
B48 |
Data 8 |
A48 |
+5v |
B49 |
Data 9 |
A49 |
Data 10 |
B50 |
Ground |
A50 |
Data 11 |
B51 |
Data 12 |
A51 |
Data 13 |
B52 |
Data 14 |
A52 |
+12v |
B53 |
Data 15 |
A53 |
DPAR 1 |
B54 |
Ground |
A54 |
-SBHE |
B55 |
-IRQ 10 |
A55 |
-CD DS 16 |
B56 |
-IRQ 11 |
A56 |
+5v |
B57 |
-IRQ 12 |
A57 |
-IRQ 14 |
B58 |
Ground |
A58 |
-IRQ 15 |
|
Access key |
|
Access key |
B59 |
Reserved |
A59 |
Reserved |
B60 |
Reserved |
A60 |
Reserved |
B61 |
-SDR 1 |
A61 |
Ground |
B62 |
-MSDR |
A62 |
Reserved |
B63 |
Ground |
A63 |
Reserved |
B64 |
Data 16 |
A64 |
-SFDBKRTN |
B65 |
Data 17 |
A65 |
+12v |
B66 |
Data 18 |
A66 |
Data 19 |
B67 |
Ground |
A67 |
Data 20 |
B68 |
Data 22 |
A68 |
Data 21 |
B69 |
Data 23 |
A69 |
+5v |
B70 |
DPAR 2 |
A70 |
Data 24 |
B71 |
Ground |
A71 |
Data 25 |
B72 |
Data 27 |
A72 |
Data 26 |
B73 |
Data 28 |
A73 |
+5v |
B74 |
Data 29 |
A74 |
Data 30 |
B75 |
Ground |
A75 |
Data 31 |
B76 |
-BE 0 |
A76 |
DPAR 3 |
B77 |
-BE 1 |
A77 |
+12v |
B78 |
-BE 2 |
A78 |
-BE 3 |
B79 |
Ground |
A79 |
-DS 32 RTN |
B80 |
TR32 |
A80 |
-CD DS 32 |
B81 |
Address 24 |
A81 |
+5v |
B82 |
Address 25 |
A82 |
Address 26 |
B83 |
Ground |
A83 |
Address 27 |
B84 |
Address 29 |
A84 |
Address 28 |
B85 |
Address 30 |
A85 |
+5v |
B86 |
Address 31 |
A86 |
-APAREN |
B87 |
Ground |
A87 |
APAR 0 |
B88 |
APAR 2 |
A88 |
APAR 1 |
B89 |
APAR 3 |
A89 |
Ground |
A = Component side, B = Back side
Figure 5.5 shows how these pins are oriented in the expansion slot.
FIG. 5.5 The MCA bus connector.
Note that for 16-bit cards only pins A01/B01 till A58/B58 are used. 32-bit cards use the full length of the connector.
Development has stopped for MCA devices due to the other faster and more feature-rich buses that became available.
The EISA Bus
EISA is an acronym for Extended Industry Standard Architecture. This standard was announced in September
1988 as a response to IBM's introduction of the MCA bus--more specifically, to the way that IBM wanted to handle licensing
of the MCA bus. Vendors did not feel obligated to pay retroactive royalties on the ISA bus, so they turned their backs on
IBM and created their own buses.
The EISA standard was developed primarily by Compaq, and was intended as being their way of taking over future development
of the PC bus away from IBM. Compaq knew that nobody would clone their bus if they were the only company that had it, so they
essentially gave the design away to other leading manufacturers. They formed the EISA Committee, a non-profit organization
designed specifically to control development of the EISA bus. Very few EISA adapters were ever developed. Those that were
developed centered mainly around disk array controllers and server type network cards.
The EISA bus provides 32-bit slots for use with 386DX or higher systems. The EISA slot enables manufacturers to design
adapter cards that have many of the capabilities of MCA adapters, but the bus also supports adapter cards created for the
older ISA standard. EISA provides markedly faster hard drive throughput when used with devices such as SCSI bus-mastering
hard drive controllers. Compared with 16-bit ISA system architecture, EISA permits greater system expansion with fewer adapter
conflicts.
The EISA bus adds 90 new connections (55 new signals) without increasing the physical connector size of the 16-bit ISA
bus. At first glance, the 32-bit EISA slot looks much like the 16-bit ISA slot. The EISA adapter, however, has two rows of
connectors. The first row is the same kind used in 16-bit ISA cards; the other, thinner row extends from the 16-bit connectors.
This means that ISA cards can still be used in EISA bus slots. Although this compatability was not enough to ensure the popularity
of EISA buses, it is a feature that was carried over into the newer VL-bus standard.
The physical specifications of an EISA card are as follows:
5 inches (127mm) high 13.13 inches (333.5mm) long 0.5 inches (12.7mm) wide
The EISA bus can handle up to 32 bits of data at an 8.33MHz cycle rate. Most data transfers require a minimum of two cycles,
although faster cycle rates are possible if an adapter card provides tight timing specifications. The maximum bandwidth on
the bus is 33M/sec, as the following formula shows:
8.33MHz x 32 bits = 266.56Mbit/sec 266.56Mbit/sec ÷ 8 = 33.32M/sec
Data transfers through an 8- or 16-bit expansion card across the bus would be reduced appropriately. Remember, however,
that these figures represent theoretical maximums. Wait states, interrupts, and other protocol factors can reduce the effective
bandwidth--typically, by half.
Table 5.5 describes the pinouts for the EISA bus. Figure 5.6 shows the locations of the pins.
Table 5.5 Pinouts for the EISA Bus
Lower Pin |
Signal Name |
Upper Pin |
Signal Name |
Upper Pin |
Signal Name |
Lower Pin |
Signal Name |
F1 |
-CMD |
A1 |
-I/O CH CHK |
B1 |
Ground |
E1 |
Ground |
F2 |
-START |
A2 |
Data 7 |
B2 |
RESET DRV |
E2 |
+5v |
F3 |
EXRDY |
A3 |
Data 6 |
B3 |
+5v |
E3 |
+5v |
F4 |
-EX32 |
A4 |
Data 5 |
B4 |
IRQ 9 |
E4 |
Reserved |
F5 |
Ground |
A5 |
Data 4 |
B5 |
-5v |
E5 |
Reserved |
F6 |
Access key |
A6 |
Data 3 |
B6 |
DRQ 2 |
E6 |
Access key |
F7 |
-EX16 |
A7 |
Data 2 |
B7 |
-12v |
E7 |
Reserved |
F8 |
-SLBURST |
A8 |
Data 1 |
B8 |
-0 WAIT |
E8 |
Reserved |
F9 |
-MSBURST |
A9 |
Data 0 |
B9 |
+12v |
E9 |
+12v |
F10 |
W-R |
A10 |
-I/O CH RDY |
B10 |
Ground |
E10 |
M-IO |
F11 |
Ground |
A11 |
AEN |
B11 |
-SMEMW |
E11 |
-LOCK |
F12 |
Reserved |
A12 |
Address 19 |
B12 |
-SMEMR |
E12 |
Reserved |
F13 |
Reserved |
A13 |
Address 18 |
B13 |
-IOW |
E13 |
Ground |
F14 |
Reserved |
A14 |
Address 17 |
B14 |
-IOR |
E14 |
Reserved |
F15 |
Ground |
A15 |
Address 16 |
B15 |
-DACK 3 |
E15 |
-BE 3 |
F16 |
Access key |
A16 |
Address 15 |
B16 |
DRQ 3 |
E16 |
Access key |
F17 |
-BE 1 |
A17 |
Address 14 |
B17 |
-DACK 1 |
E17 |
-BE 2 |
F18 |
Latch address 31 |
A18 |
Address 13 |
B18 |
DRQ 1 |
E18 |
-BE 0 |
F19 |
Ground |
A19 |
Address 12 |
B19 |
-REFRESH |
E19 |
Ground |
F20 |
-Latch address 30 |
A20 |
Address 11 |
B20 |
CLK (8.33MHz) |
E20 |
+5v |
F21 |
-Latch address 28 |
A21 |
Address 10 |
B21 |
IRQ 7 |
E21 |
Latch address 29 |
F22 |
-Latch address 27 |
A22 |
Address 9 |
B22 |
IRQ 6 |
E22 |
Ground |
F23 |
-Latch address 25 |
A23 |
Address 8 |
B23 |
IRQ 5 |
E23 |
Latch address 26 |
F24 |
Ground |
A24 |
Address 7 |
B24 |
IRQ 4 |
E24 |
Latch address 24 |
F25 |
Access key |
A25 |
Address 6 |
B25 |
IRQ 3 |
E25 |
Access key |
F26 |
Latch address 15 |
A26 |
Address 5 |
B26 |
-DACK 2 |
E26 |
Latch address 16 |
F27 |
Latch address 13 |
A27 |
Address 4 |
B27 |
T/C |
E27 |
Latch address 14 |
F28 |
Latch address 12 |
A28 |
Address 3 |
B28 |
BALE |
E28 |
+5v |
F29 |
Latch address 11 |
A29 |
Address 2 |
B29 |
+5v |
E29 |
+5v |
F30 |
Ground |
A30 |
Address 1 |
B30 |
OSC (14.3MHz) |
E30 |
Ground |
F31 |
Latch address 9 |
A31 |
Address 0 |
B31 |
Ground |
E31 |
Latch address 10 |
|
Access key |
|
Access key |
|
Access key |
|
Access key |
H1 |
Latch address 7 |
C1 |
-SBHE |
D1 |
-MEM CS16 |
G1 |
Latch address 8 |
H2 |
Ground |
C2 |
Latch address 23 |
D2 |
-I/O CS16 |
G2 |
Latch address 6 |
H3 |
Latch address 4 |
C3 |
Latch address 22 |
D3 |
IRQ 10 |
G3 |
Latch address 5 |
H4 |
Latch address 3 |
C4 |
Latch address 21 |
D4 |
IRQ 11 |
G4 |
+5v |
H5 |
Ground |
C5 |
Latch address 20 |
D5 |
IRQ 12 |
G5 |
Latch address 4 |
H6 |
Access key |
C6 |
Latch address 19 |
D6 |
IRQ 15 |
G6 |
Access key |
H7 |
Data 17 |
C7 |
Latch address 18 |
D7 |
IRQ 14 |
G7 |
Data 16 |
H8 |
Data 19 |
C8 |
Latch address 17 |
D8 |
-DACK 0 |
G8 |
Data 18 |
H9 |
Data 20 |
C9 |
-MEMR |
D9 |
DRQ 0 |
G9 |
Ground |
H10 |
Data 22 |
C10 |
-MEMW |
D10 |
-DACK 5 |
G10 |
Data 21 |
H11 |
Ground |
C11 |
Data 8 |
D11 |
DRQ 5 |
G11 |
Data 23 |
H12 |
Data 25 |
C12 |
Data 9 |
D12 |
-DACK 6 |
G12 |
Data 24 |
H13 |
Data 26 |
C13 |
Data 10 |
D13 |
DRQ 6 |
G13 |
Ground |
H14 |
Data 28 |
C14 |
Data 11 |
D14 |
-DACK 7 |
G14 |
Data 27 |
H15 |
Access key |
C15 |
Data 12 |
D15 |
DRQ 7 |
G15 |
Access key |
H16 |
Ground |
C16 |
Data 13 |
D16 |
+5v |
G16 |
Data 29 |
H17 |
Data 30 |
C17 |
Data 14 |
D17 |
-MASTER |
G17 |
+5v |
H18 |
Data 31 |
C18 |
Data 15 |
D18 |
Ground |
G18 |
+5v |
H19 |
-MREQx |
|
|
|
|
G19 |
-MAKx |
A/C = Component side top, B/D = Back side top F/H = Component side bottom, E/G = Back side bottom
FIG. 5.6 The card connector for the EISA bus.
EISA systems also use an automated setup to deal with adapter-board interrupts and addressing issues. These issues often
cause problems when several different adapter boards are installed in an ISA system. EISA setup software recognizes potential
conflicts and automatically configures the system to avoid them. EISA does, however, enable you to do your own troubleshooting,
as well as to configure the boards through jumpers and switches. This concept was not new to EISA; IBM's MCA bus also supported
configuration via software. Another new feature of EISA systems is IRQ sharing, meaning that multiple bus cards can share
a single interrupt. This feature has also been implemented in PCI bus cards.
NOTE:Although automated setup traditionally has not been available in ISA systems, it became
available with Plug and Play (PnP) systems and components. PnP systems are discussed toward the end of this chapter in the
section "Plug and Play Systems."
The PC Card Bus
In an effort to give laptop and notebook computers the kind of expandability that users have grown used to in desktop systems,
the Personal Computer Memory Card International Association (PCMCIA) has established several standards for credit card-size
expansion boards that fit into a small slot on laptops and notebooks. The development of the PC Card interface is one of the
few successful feats of hardware standardization in a market full of proprietary designs.
The PC Card standards, which were developed by a consortium of more than 300 manufacturers (including IBM, Toshiba, and
Apple), have been touted as being a revolutionary advancement in mobile computing. PC Card laptop and notebook slots enable
you to add memory expansion cards, fax/modems, SCSI adapters, network interface adapters, and many other types of devices.
If your computer has PC Card slots that conform to the standard developed by the PCMCIA, you can insert any type of PC Card
(built to the same standard) into your machine and expect it to be recognized and usable. You will find PC Card bus systems
mostly in laptop systems, because of the small credit card-size.
NOTE: For more information on the PC Card bus, see Chapter 19 - Portable Systems.
Local Buses
The I/O buses discussed so far (ISA, MCA, EISA and PC Card) have one thing in common: relatively slow speed. This speed
limitation is a carryover from the days of the original PC, when the I/O bus operated at the same speed as the processor bus.
As the speed of the processor bus increased, the I/O bus realized only nominal speed improvements, primarily from an increase
in the bandwidth of the bus. The I/O bus had to remain at a slower speed, because the huge installed base of adapter cards
could operate only at slower speeds.
Figure 5.7 shows a conceptual block diagram of the buses in a computer system.
FIG. 5.7 Bus layout in a traditional PC.
The thought of a computer system running slower than it could is very bothersome to some computer users. Even so, the slow
speed of the I/O bus is nothing more than a nuisance in most cases. You don't need blazing speed to communicate with a keyboard
or a mouse, for example; you gain nothing in performance. The real problem occurs in subsystems in which you need the speed,
such as video and disk controllers.
The speed problem became acute when graphical user interfaces (such as Windows) became prevalent. These systems required
the processing of so much video data that the I/O bus became a literal bottleneck for the entire computer system. In other
words, it did little good to have a CPU that was capable of 66MHz speed if you could put data through the I/O bus at a rate
of only 8MHz.
An obvious solution to this problem is to move some of the slotted I/O to an area where it could access the faster speeds
of the processor bus--much the same way as the external cache. Figure 5.8 shows this arrangement.
FIG. 5.8 How a local bus works.
This arrangement became known as local bus, because external devices (adapter cards) now could access the part of
the bus that was local to the CPU--the processor bus. Physically, the slots provided to tap this new configuration would need
to be different from existing bus slots, to prevent adapter cards designed for slower buses from being plugged into the higher
bus speeds that this design made accessible.
It is interesting to note that the very first 8-bit and 16-bit ISA buses were a form of Local Bus architecture. These systems
had the processor bus as the main bus, and everything ran at full processor speeds. When ISA systems ran faster than 8MHz,
the main ISA bus had to be decoupled from the processor bus since expansion cards, memory, and so on could not keep up. In
1992, an extension to the ISA bus called the VESA Local Bus started showing up on PC systems, indicating a return to
Local Bus architecture.
NOTE: A system does not have to have a local-bus expansion slot to incorporate local-bus
technology; instead, the local-bus device can be built directly into the motherboard. (In such a case, the local-bus-slotted
I/O shown in Figure 5.11 would in fact be built-in I/O.) This built-in approach to local bus is the way the first local-bus
systems were designed.
Local-bus systems became especially popular with users of Windows and OS/2, because these slots first were used for special
32-bit video accelerator cards that greatly speed the repainting of the graphics screens used in those operating systems.
The performance of Windows and OS/2 suffers greatly from bottlenecks in even the best VGA cards connected to an ISA or EISA
bus.
This section discusses the newer local bus technologies:
- VESA Local Bus (VL-Bus)
- The PCI Bus
- The AGP Bus
- FireWire (IEEE 1394)
- USB
VESA Local Bus
The VESA Local Bus was the most popular local bus design from its debut in August 1992 through 1994. It was created by
the VESA committee, a non-profit organization founded by NEC to further develop video display and bus standards. In a similar
fashion to how EISA evolved, NEC had done most of the work on the VL-bus (as it would be called) and, after founding the non-profit
VESA committee, they turned over future development to VESA. At first, the local-bus slot seemed primarily designed to be
used for video cards. Improving video performance was a top priority at NEC to help sell their high-end displays as well as
their own PC systems. By 1991, video performance had become a real bottleneck in most PC systems.
The Video Electronics Standards Association (VESA) developed a standardized local-bus specification known as VESA Local
Bus or simply VL-Bus. As in earlier local-bus implementations, the VL-Bus slot offers direct access to system memory
at the speed of the processor itself. The VL-Bus can move data 32 bits at a time, enabling data to flow between the CPU and
a compatible video subsystem or hard drive at the full 32-bit data width of the 486 chip. The maximum rated throughput of
the VL-Bus is 132M/sec. In other words, local bus went a long way toward removing the major bottlenecks that existed in earlier
bus configurations.
Additionally, VL-Bus offers manufacturers of hard-drive interface cards an opportunity to overcome another traditional
bottleneck: the rate at which data can flow between the hard drive and the CPU. The average 16-bit IDE drive and interface
can achieve throughput of up to 5M/sec, whereas VL-Bus hard drive adapters for IDE drives are touted as providing throughput
of as much as 8M/sec. In real-world situations, the true throughput of VL-Bus hard drive adapters is somewhat less than 8M/sec,
but VL-Bus still provides a substantial boost in hard-drive performance.
Despite all the benefits of the VL-Bus (and, by extension, of all local buses), this tech-nology has a few drawbacks, which
are described in the following list:
- Dependence on a 486 CPU. The VL-Bus inherently is tied to the 486 processor bus. This bus is quite different from
that used by Pentium processors. A VL-Bus that operates at the full-rated speed of a Pentium has not been developed, although
stopgap measures (such as stepping down speed or developing bus bridges) are available. Unfortunately, these result in poor
performance. Some systems have been developed with both VL-Bus and PCI slots, but because of design compromises, performance
often suffers.
- Speed limitations. The VL-Bus specification provides for speeds of up to 66MHz on the bus, but the electrical characteristics
of the VL-Bus connector limit an adapter card to no more than 40 to 50MHz. In practice, running the VL-Bus at speeds over
33MHz causes many problems, so 33MHz has become the acceptable speed limit. Systems that use faster processor bus speeds must
buffer and step down the clock on the VL-Bus or add wait states. Note that if the main CPU uses a clock modifier (such as
the kind that doubles clock speeds), the VL-Bus uses the unmodified CPU clock speed as its bus speed.
- Electrical limitations. The processor bus has very tight timing rules, which may vary from CPU to CPU. These timing
rules were designed for limited loading on the bus, meaning that the only elements originally intended to be connected to
the local bus are elements such as the external cache and the bus controller chips. As you add more circuitry, you increase
the electrical load. If the local bus is not implemented correctly, the additional load can lead to problems such as loss
of data integrity and timing problems between the CPU and the VL-Bus cards.
- Card limitations. Depending on the electrical loading of a system, the number of VL-Bus cards is limited. Although
the VL-Bus specification provides for as many as three cards, this can be achieved only at clock rates of up to 40MHz with
an otherwise low system-board load. As the system-board load increases and the clock rate increases, the number of cards supported
decreases. Only one VL-Bus card can be supported at 50MHz with a high system-board load. In practice, these limits could not
usually be reached without problems.
The VL-Bus did not seem to be a well-engineered concept. The design was simple indeed--just take the pins from the 486
processor and run them out to a card connector socket. In other words, the VL-Bus is essentially the raw 486 processor bus.
This allowed a very inexpensive design, since no additional chipsets or interface chips were required. A motherboard designer
could add VL-Bus slots to their 486 motherboards very easily and at a very low cost. This is why these slots appeared on virtually
all 486 system designs overnight.
Unfortunately, the 486 processor bus was not designed to have multiple devices (called loads) plugged into it at
one time. Problems arose with timing glitches caused by the capacitance introduced into the circuit by different cards. Since
the VL-Bus ran at the same speed as the processor bus, different processor speeds meant different bus speeds, and full compatibility
was difficult to achieve. Although the VL-Bus could be adapted to other processors, including the 386 or even the Pentium,
it was designed for the 486, and worked best as a 486 solution only. Despite the low cost, after a new bus called PCI (Peripheral
Component Interconnect) appeared, VL-Bus fell into disfavor very quickly. It never did catch on with Pentium systems,
and there was little or no further development of the VL-Bus in the PC industry.
Physically, the VL-Bus slot is an extension of the slots used for whatever type of base system you have. If you have an
ISA system, the VL-Bus is positioned as an extension of your existing 16-bit ISA slots. Likewise, if you have an EISA system
or MCA system, the VL-Bus slots are extensions of those existing slots. Figure 5.9 shows how the VL-Bus slots could be situated
in an ISA system. The VESA extension uses the same physical connector as the MCA bus.
FIG. 5.9 An example of VL-Bus slots in an ISA system.
The specification also includes an optional 64-bit mode. The 64-bit expansion of the bus does not add additional pins or
connectors. Instead, it multiplexes the existing pins. For example, the pins B21 to B40 feed multiplexed address / data signals
in 64-bit mode.
The VL-Bus adds a total 116 pin locations to the bus connectors that your system already has. Table 5.6 lists the pinouts
for only the VL-Bus connector portion of the total connector. For pins for which two purposes are listed, the second purpose
applies when the card is in 64-bit transfer mode.
Table 5.6 Pinouts for the VL-Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
Data 0 |
A1 |
Data 1 |
B2 |
Data 2 |
A2 |
Data 3 |
B3 |
Data 4 |
A3 |
Ground |
B4 |
Data 6 |
A4 |
Data 5 |
B5 |
Data 8 |
A5 |
Data 7 |
B6 |
Ground |
A6 |
Data 9 |
B7 |
Data 10 |
A7 |
Data 11 |
B8 |
Data 12 |
A8 |
Data 13 |
B9 |
+5v |
A9 |
Data 15 |
B10 |
Data 14 |
A10 |
Ground |
B11 |
Data 16 |
A11 |
Data 17 |
B12 |
Data 18 |
A12 |
+5v |
B13 |
Data 20 |
A13 |
Data 19 |
B14 |
Ground |
A14 |
Data 21 |
B15 |
Data 22 |
A15 |
Data 23 |
B16 |
Data 24 |
A16 |
Data 25 |
B17 |
Data 26 |
A17 |
Ground |
B18 |
Data 28 |
A18 |
Data 27 |
B19 |
Data 30 |
A19 |
Data 29 |
B20 |
+5v |
A20 |
Data 31 |
B21 |
Address 31 / Data 63 |
A21 |
Address 30 / Data 62 |
B22 |
Ground |
A22 |
Address 28 / Data 60 |
B23 |
Address 29 / Data 61 |
A23 |
Address 26 / Data 58 |
B24 |
Address 27 / Data 59 |
A24 |
Ground |
B25 |
Address 25 / Data 57 |
A25 |
Address 24 / Data 56 |
B26 |
Address 23 / Data 55 |
A26 |
Address 22 / Data 54 |
B27 |
Address 21 / Data 53 |
A27 |
+5v |
B28 |
Address 19 / Data 51 |
A28 |
Address 20 / Data 52 |
B29 |
Ground |
A29 |
Address 18 / Data 50 |
B30 |
Address 17 / Data 49 |
A30 |
Address 16 / Data 48 |
B31 |
Address 15 / Data 47 |
A31 |
Address 14 / Data 46 |
B32 |
+5v |
A32 |
Address 12 / Data 44 |
B33 |
Address 13 / Data 45 |
A33 |
Address 10 / Data 42 |
B34 |
Address 11 / Data 43 |
A34 |
Address 8 / Data 40 |
B35 |
Address 9 / Data 41 |
A35 |
Ground |
B36 |
Address 7 / Data 39 |
A36 |
Address 6 / Data 38 |
B37 |
Address 5 / Data 37 |
A37 |
Address 4 / Data 36 |
B38 |
Ground |
A38 |
-WBACK |
B39 |
Address 3 / Data 35 |
A39 |
-BE 0 / -BE 4 |
B40 |
Address 2 / Data 34 |
A40 |
+5v |
B41 |
Reserved / -LBS64 |
A41 |
-BE 1 / -BE 5 |
B42 |
-RESET |
A42 |
-BE 2 / -BE 6 |
B43 |
-DC |
A43 |
Ground |
B44 |
-M/IO / Data 33 |
A44 |
-BE 3 / -BE 7 |
B45 |
-W/R / Data 32 |
A45 |
-ADS |
B46 |
Access key |
A46 |
Access key |
B47 |
Access key |
A47 |
Access key |
B48 |
-RDYRTN |
A48 |
-LRDY |
B49 |
Ground |
A49 |
LDEV |
B50 |
IRQ 9 |
A50 |
LREQ |
B51 |
-BRDY |
A51 |
Ground |
B52 |
-BLAST |
A52 |
LGNT |
B53 |
ID 0 |
A53 |
+5v |
B54 |
ID 1 |
A54 |
ID 2 |
B55 |
Ground |
A55 |
ID 3 |
B56 |
LCLK |
A56 |
ID 4 / -ACK64 |
B57 |
+5v |
A57 |
-LKEN |
B58 |
-LBS16 |
A58 |
-LEADS |
A = Component side, B = Back side For pins for which two purposes are listed, the second purpose applies when the
card is in 64-bit transfer mode.
Figure 5.10 shows the locations of the pins.
FIG. 5.10 The card connector for the VL-Bus.
The PCI Bus
In early 1992, Intel spearheaded the creation of another industry group. It was formed with the same goals as the VESA
group in relation to the PC bus. Recognizing the need to overcome weaknesses in the ISA and EISA buses, the PCI Special
Interest Group was formed.
PCI is an acronym for Peripheral Component Interconnect. The PCI bus specification, released in June 1992
and updated in April 1993 to version 2.0, redesigned the traditional PC bus by inserting another bus between the CPU and the
native I/O bus by means of bridges. Rather than tap directly into the processor bus, with its delicate electrical timing (as
was done in the VL-Bus), a new set of controller chips was developed to extend the bus, as shown in Figure 5.11.
FIG. 5.11 Conceptual diagram of the PCI bus.
The PCI bus often is called a mezzanine bus because it adds another layer to the traditional bus configuration.
PCI bypasses the standard I/O bus; it uses the system bus to increase the bus clock speed and take full advantage of the CPU's
data path. Systems that integrate the PCI bus became available in mid 1993.
Information is transferred across the PCI bus at 33MHz, at the full data width of the CPU. When the bus is used in conjunction
with a 32-bit CPU, the bandwidth is 132M per second, as the following formula shows:
33MHz x 32 bits = 1,056Mbit/sec 1,056Mbit/sec ÷ 8 = 132M/sec
When the bus is used in 64-bit implementations, the bandwidth doubles, meaning that you can transfer data at speeds up
to 264M/sec. Real-life data transfer speeds necessarily will be lower, but still much faster than anything else that was available.
Part of the reason for this faster real-life throughput is the fact that the PCI bus can operate concurrently with the processor
bus; it does not supplant it. The CPU can be processing data in an external cache while the PCI bus is busy transferring information
between other parts of the system--a major design benefit of the PCI bus.
A PCI adapter card uses its own unique connector. This connector can be identified within a computer system because it
typically is offset from the normal ISA, MCA, or EISA connectors. See Figure 5.12 for an example. The size of a PCI card can
be the same as that of the cards used in the system's normal I/O bus.
FIG. 5.12 Possible configuration of PCI slots in relation to ISA or EISA slots.
The PCI specification identifies three board configurations, each designed for a specific type of system with specific
power requirements. The 5v specification is for stationary computer systems, the 3.3v specification is for portable machines,
and the universal specification is for motherboards and cards that work in either type of system.
Notice that the universal PCI board specifications effectively combine the 5v and 3.3v specifications. For pins for which
the voltage is different, the universal specification labels the pin simply V I/O. This type of pin represents a special power
pin for defining and driving the PCI signaling rail.
Another important feature of PCI is the fact that it was the model for the Intel PnP specification. This means that PCI
cards do not have jumpers and switches, and are instead configured through software. True PnP systems are able to automatically
configure the adapters, while non-PnP systems with ISA slots have to configure the adapters through a program that is usually
a part of the system CMOS configuration. Starting in late 1995, most PC-compatible systems have included a PnP BIOS that allows
the automatic PnP configuration.
PCI 2.1
In June 1995, the PCI specification was revised to version 2.1. The main improvement of the PCI 2.1 specification is the
ability to operate at 66MHz, doubling the data transfer rate to 512M/sec in 64-bit mode. The PCI 2.1 standard is backward-compatible
with 33MHz PCI devices and buses. If a 66MHz capable PCI is installed in a 33MHz bus, the device operates at 33MHz. Likewise,
if any 33MHz PCI devices are installed into a 66MHz bus, the PCI bus operates at 33MHz. Only 3.3v devices can be capable of
operating at 66MHz. In the PCI 2.1 bus, pin B49 has been defined as the M66EN (66MHz enable) pin. For 5v devices, this pin
remains a Ground pin.
PCI 2.2
In December 1998, version 2.2 of the PCI specification was released. PCI 2.2 incorporates many minor clarifications and
enhancements. All cache support was removed, therefore the pins A40 and A41 were defined as Reserved.
PCI 2.3
PCI 2.3 was released in 2001, adding some new features to the standard. One of the improvements is the support for System
Management Bus (SM Bus). The SM Bus is a two-wire management interface, providing the ability to manage a variety of features.
Another new function is the Interrupt Status Bit, which can be checked by the operating system to determine which of
the cards need servicing, in case of interrupt sharing. This reduces the overhead required to handle interrupt sharing, and
reduces the associated latency. In the PCI 2.3 specification, pin A40 is defined as SMBCLK (SM Bus Clock), and pin A41 is
defined as SMBDAT (SM Bus Data). Both pins were reserved in the PCI 2.2 specification, because the cache support was removed.
Table 5.7 shows the 5v PCI pinouts, and Figure 5.13 shows the pin locations. Table 5.8 shows the 3.3v PCI pinouts; the
pin locations are indicated in Figure 5.14. Finally, Table 5.9 shows the pinouts, and Figure 5.15 shows the pin locations
for a universal PCI slot and card. Notice that each figure shows both the 32-bit and 64-bit variations on the respective specifications.
NOTE: If the PCI card supports only 32 data bits, it needs only pins B1/A1 through B62/A62.
Pins B63/A63 through B94/A94 are used only if the card supports 64 data bits.
Table 5.7 Pinouts for a 5v PCI Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
-12v |
A1 |
-TRST |
B2 |
TCK |
A2 |
+12v |
B3 |
Ground |
A3 |
TMS |
B4 |
TDO |
A4 |
TDI |
B5 |
+5v |
A5 |
+5v |
B6 |
+5v |
A6 |
-INT A |
B7 |
-INT B |
A7 |
-INT C |
B8 |
-INT D |
A8 |
+5v |
B9 |
-PRSNT1 |
A9 |
Reserved |
B10 |
Reserved |
A10 |
+5v I/O |
B11 |
-PRSNT2 |
A11 |
Reserved |
B12 |
Ground |
A12 |
Ground |
B13 |
Ground |
A13 |
Ground |
B14 |
Reserved |
A14 |
Reserved |
B15 |
Ground |
A15 |
-RST |
B16 |
CLK |
A16 |
+5v I/O |
B17 |
Ground |
A17 |
-GNT |
B18 |
-REQ |
A18 |
Ground |
B19 |
+5v I/O |
A19 |
Reserved |
B20 |
Address/Data 31 |
A20 |
Address/Data 30 |
B21 |
Address/Data 29 |
A21 |
+3.3v |
B22 |
Ground |
A22 |
Address/Data 28 |
B23 |
Address/Data 27 |
A23 |
Address/Data 26 |
B24 |
Address/Data 25 |
A24 |
Ground |
B25 |
+3.3v |
A25 |
Address/Data 24 |
B26 |
-C/BE 3 |
A26 |
IDSEL |
B27 |
Address/Data 23 |
A27 |
+3.3v |
B28 |
Ground |
A28 |
Address/Data 22 |
B29 |
Address/Data 21 |
A29 |
Address/Data 20 |
B30 |
Address/Data 19 |
A30 |
Ground |
B31 |
+3.3v |
A31 |
Address/Data 18 |
B32 |
Address/Data 17 |
A32 |
Address/Data 16 |
B33 |
-C/BE 2 |
A33 |
+3.3v |
B34 |
Ground |
A34 |
-FRAME |
B35 |
-IRDY |
A35 |
Ground |
B36 |
+3.3v |
A36 |
-TRDY |
B37 |
-DEVSEL |
A37 |
Ground |
B38 |
Ground |
A38 |
-STOP |
B39 |
-LOCK |
A39 |
+3.3v |
B40 |
-PERR |
A40 |
SDONE / Reserved / SMBCLK * |
B41 |
+3.3v |
A41 |
-SBO / Reserved / SMBDAT ** |
B42 |
-SERR |
A42 |
Ground |
B43 |
+3.3v |
A43 |
PAR |
B44 |
-C/BE 1 |
A44 |
Address/Data 15 |
B45 |
Address/Data 14 |
A45 |
+3.3v |
B46 |
Ground |
A46 |
Address/Data 13 |
B47 |
Address/Data 12 |
A47 |
Address/Data 11 |
B48 |
Address/Data 10 |
A48 |
Ground |
B49 |
Ground |
A49 |
Address/Data 9 |
B50 |
Access key |
A50 |
Access key |
B51 |
Access key |
A51 |
Access key |
B52 |
Address/Data 8 |
A52 |
-C/BE 0 |
B53 |
Address/Data 7 |
A53 |
+3.3v |
B54 |
+3.3v |
A54 |
Address/Data 6 |
B55 |
Address/Data 5 |
A55 |
Address/Data 4 |
B56 |
Address/Data 3 |
A56 |
Ground |
B57 |
Ground |
A57 |
Address/Data 2 |
B58 |
Address/Data 1 |
A58 |
Address/Data 0 |
B59 |
+5v I/O |
A59 |
+5v I/O |
B60 |
-ACK64 |
A60 |
-REQ64 |
B61 |
+5v |
A61 |
+5v |
B62 |
+5v |
A62 |
+5v |
|
Access key |
|
Access key |
B63 |
Reserved |
A63 |
Ground |
B64 |
Ground |
A64 |
-C/BE 7 |
B65 |
-C/BE 6 |
A65 |
-C/BE 5 |
B66 |
-C/BE 4 |
A66 |
+5v I/O |
B67 |
Ground |
A67 |
PAR64 |
B68 |
Address/Data 63 |
A68 |
Address/Data 62 |
B69 |
Address/Data 61 |
A69 |
Ground |
B70 |
+5v I/O |
A70 |
Address/Data 60 |
B71 |
Address/Data 59 |
A71 |
Address/Data 58 |
B72 |
Address/Data 57 |
A72 |
Ground |
B73 |
Ground |
A73 |
Address/Data 56 |
B74 |
Address/Data 55 |
A74 |
Address/Data 54 |
B75 |
Address/Data 53 |
A75 |
+5v I/O |
B76 |
Ground |
A76 |
Address/Data 52 |
B77 |
Address/Data 51 |
A77 |
Address/Data 50 |
B78 |
Address/Data 49 |
A78 |
Ground |
B79 |
+5v I/O |
A79 |
Address/Data 48 |
B80 |
Address/Data 47 |
A80 |
Address/Data 46 |
B81 |
Address/Data 45 |
A81 |
Ground |
B82 |
Ground |
A82 |
Address/Data 44 |
B83 |
Address/Data 43 |
A83 |
Address/Data 42 |
B84 |
Address/Data 41 |
A84 |
+5v I/O |
B85 |
Ground |
A85 |
Address/Data 40 |
B86 |
Address/Data 39 |
A86 |
Address/Data 38 |
B87 |
Address/Data 37 |
A87 |
Ground |
B88 |
+5v I/O |
A88 |
Address/Data 36 |
B89 |
Address/Data 35 |
A89 |
Address/Data 34 |
B90 |
Address/Data 33 |
A90 |
Ground |
B91 |
Ground |
A91 |
Address/Data 32 |
B92 |
Reserved |
A92 |
Reserved |
B93 |
Reserved |
A93 |
Ground |
B94 |
Ground |
A94 |
Reserved |
A = Back side, B = Component side
* In the PCI 2.2 bus, pin A40 is Reserved. In the PCI 2.3 bus, pin A40 is defined as SMBCLK (SM Bus Clock). ** In
the PCI 2.2 bus, pin A41 is Reserved. In the PCI 2.3 bus, pin A41 is defined as SMBDAT (SM Bus Data).
FIG. 5.13 The 5v PCI slot and card configuration.
Table 5.8 Pinouts for a 3.3v PCI Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
-12v |
A1 |
-TRST |
B2 |
TCK |
A2 |
+12v |
B3 |
Ground |
A3 |
TMS |
B4 |
TDO |
A4 |
TDI |
B5 |
+5v |
A5 |
+5v |
B6 |
+5v |
A6 |
-INT A |
B7 |
-INT B |
A7 |
-INT C |
B8 |
-INT D |
A8 |
+5v |
B9 |
-PRSNT1 |
A9 |
Reserved |
B10 |
Reserved |
A10 |
+3.3v I/O |
B11 |
-PRSNT2 |
A11 |
Reserved |
B12 |
Access key |
A12 |
Access key |
B13 |
Access key |
A13 |
Access key |
B14 |
Reserved |
A14 |
Reserved |
B15 |
Ground |
A15 |
-RST |
B16 |
CLK |
A16 |
+3.3v I/O |
B17 |
Ground |
A17 |
-GNT |
B18 |
-REQ |
A18 |
Ground |
B19 |
+3.3v I/O |
A19 |
Reserved |
B20 |
Address/Data 31 |
A20 |
Address/Data 30 |
B21 |
Address/Data 29 |
A21 |
+3.3v |
B22 |
Ground |
A22 |
Address/Data 28 |
B23 |
Address/Data 27 |
A23 |
Address/Data 26 |
B24 |
Address/Data 25 |
A24 |
Ground |
B25 |
+3.3v |
A25 |
Address/Data 24 |
B26 |
-C/BE 3 |
A26 |
IDSEL |
B27 |
Address/Data 23 |
A27 |
+3.3v |
B28 |
Ground |
A28 |
Address/Data 22 |
B29 |
Address/Data 21 |
A29 |
Address/Data 20 |
B30 |
Address/Data 19 |
A30 |
Ground |
B31 |
+3.3v |
A31 |
Address/Data 18 |
B32 |
Address/Data 17 |
A32 |
Address/Data 16 |
B33 |
-C/BE 2 |
A33 |
+3.3v |
B34 |
Ground |
A34 |
-FRAME |
B35 |
-IRDY |
A35 |
Ground |
B36 |
+3.3v |
A36 |
-TRDY |
B37 |
-DEVSEL |
A37 |
Ground |
B38 |
Ground / PCIXCAP * |
A38 |
-STOP |
B39 |
-LOCK |
A39 |
+3.3v |
B40 |
-PERR |
A40 |
SDONE / Reserved / SMBCLK ** |
B41 |
+3.3v |
A41 |
-SBO / Reserved / SMBDAT *** |
B42 |
-SERR |
A42 |
Ground |
B43 |
+3.3v |
A43 |
PAR |
B44 |
-C/BE 1 |
A44 |
Address/Data 15 |
B45 |
Address/Data 14 |
A45 |
+3.3v |
B46 |
Ground |
A46 |
Address/Data 13 |
B47 |
Address/Data 12 |
A47 |
Address/Data 11 |
B48 |
Address/Data 10 |
A48 |
Ground |
B49 |
Ground / M66EN **** |
A49 |
Address/Data 9 |
B50 |
Ground |
A50 |
Ground |
B51 |
Ground |
A51 |
Ground |
B52 |
Address/Data 8 |
A52 |
-C/BE 0 |
B53 |
Address/Data 7 |
A53 |
+3.3v |
B54 |
+3.3v |
A54 |
Address/Data 6 |
B55 |
Address/Data 5 |
A55 |
Address/Data 4 |
B56 |
Address/Data 3 |
A56 |
Ground |
B57 |
Ground |
A57 |
Address/Data 2 |
B58 |
Address/Data 1 |
A58 |
Address/Data 0 |
B59 |
+3.3v I/O |
A59 |
+3.3v I/O |
B60 |
-ACK64 |
A60 |
-REQ64 |
B61 |
+5v |
A61 |
+5v |
B62 |
+5v |
A62 |
+5v |
|
Access key |
|
Access key |
B63 |
Reserved |
A63 |
Ground |
B64 |
Ground |
A64 |
-C/BE 7 |
B65 |
-C/BE 6 |
A65 |
-C/BE 5 |
B66 |
-C/BE 4 |
A66 |
+3.3v I/O |
B67 |
Ground |
A67 |
PAR64 |
B68 |
Address/Data 63 |
A68 |
Address/Data 62 |
B69 |
Address/Data 61 |
A69 |
Ground |
B70 |
+3.3v I/O |
A70 |
Address/Data 60 |
B71 |
Address/Data 59 |
A71 |
Address/Data 58 |
B72 |
Address/Data 57 |
A72 |
Ground |
B73 |
Ground |
A73 |
Address/Data 56 |
B74 |
Address/Data 55 |
A74 |
Address/Data 54 |
B75 |
Address/Data 53 |
A75 |
+3.3v I/O |
B76 |
Ground |
A76 |
Address/Data 52 |
B77 |
Address/Data 51 |
A77 |
Address/Data 50 |
B78 |
Address/Data 49 |
A78 |
Ground |
B79 |
+3.3v I/O |
A79 |
Address/Data 48 |
B80 |
Address/Data 47 |
A80 |
Address/Data 46 |
B81 |
Address/Data 45 |
A81 |
Ground |
B82 |
Ground |
A82 |
Address/Data 44 |
B83 |
Address/Data 43 |
A83 |
Address/Data 42 |
B84 |
Address/Data 41 |
A84 |
+3.3v I/O |
B85 |
Ground |
A85 |
Address/Data 40 |
B86 |
Address/Data 39 |
A86 |
Address/Data 38 |
B87 |
Address/Data 37 |
A87 |
Ground |
B88 |
+3.3v I/O |
A88 |
Address/Data 36 |
B89 |
Address/Data 35 |
A89 |
Address/Data 34 |
B90 |
Address/Data 33 |
A90 |
Ground |
B91 |
Ground |
A91 |
Address/Data 32 |
B92 |
Reserved |
A92 |
Reserved |
B93 |
Reserved |
A93 |
Ground |
B94 |
Ground |
A94 |
Reserved |
A = Back side, B = Component side
* In the PCI-X bus, pin B38 is defined as PCIXCAP. ** In the PCI 2.2 bus, pin A40 is Reserved. In the PCI 2.3 bus,
pin A40 is defined as SMBCLK (SM Bus Clock). *** In the PCI 2.2 bus, pin A41 is Reserved. In the PCI 2.3 bus, pin A41 is
defined as SMBDAT (SM Bus Data). **** In the PCI 2.1 bus, pin B49 has been defined as the M66EN (66MHz enable) pin.
FIG. 5.14 The 3.3v PCI slot and card configuration.
Table 5.9 Pinouts for a Universal PCI Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
-12v |
A1 |
-TRST |
B2 |
TCK |
A2 |
+12v |
B3 |
Ground |
A3 |
TMS |
B4 |
TDO |
A4 |
TDI |
B5 |
+5v |
A5 |
+5v |
B6 |
+5v |
A6 |
-INT A |
B7 |
-INT B |
A7 |
-INT C |
B8 |
-INT D |
A8 |
+5v |
B9 |
-PRSNT1 |
A9 |
Reserved |
B10 |
Reserved |
A10 |
+v I/O |
B11 |
-PRSNT2 |
A11 |
Reserved |
B12 |
Access key |
A12 |
Access key |
B13 |
Access key |
A13 |
Access key |
B14 |
Reserved |
A14 |
Reserved |
B15 |
Ground |
A15 |
-RST |
B16 |
CLK |
A16 |
+v I/O |
B17 |
Ground |
A17 |
-GNT |
B18 |
-REQ |
A18 |
Ground |
B19 |
+v I/O |
A19 |
Reserved |
B20 |
Address/Data 31 |
A20 |
Address/Data 30 |
B21 |
Address/Data 29 |
A21 |
+3.3v |
B22 |
Ground |
A22 |
Address/Data 28 |
B23 |
Address/Data 27 |
A23 |
Address/Data 26 |
B24 |
Address/Data 25 |
A24 |
Ground |
B25 |
+3.3v |
A25 |
Address/Data 24 |
B26 |
-C/BE 3 |
A26 |
IDSEL |
B27 |
Address/Data 23 |
A27 |
+3.3v |
B28 |
Ground |
A28 |
Address/Data 22 |
B29 |
Address/Data 21 |
A29 |
Address/Data 20 |
B30 |
Address/Data 19 |
A30 |
Ground |
B31 |
+3.3v |
A31 |
Address/Data 18 |
B32 |
Address/Data 17 |
A32 |
Address/Data 16 |
B33 |
-C/BE 2 |
A33 |
+3.3v |
B34 |
Ground |
A34 |
-FRAME |
B35 |
-IRDY |
A35 |
Ground |
B36 |
+3.3v |
A36 |
-TRDY |
B37 |
-DEVSEL |
A37 |
Ground |
B38 |
Ground / PCIXCAP * |
A38 |
-STOP |
B39 |
-LOCK |
A39 |
+3.3v |
B40 |
-PERR |
A40 |
SDONE / Reserved / SMBCLK ** |
B41 |
+3.3v |
A41 |
-SBO / Reserved / SMBDAT *** |
B42 |
-SERR |
A42 |
Ground |
B43 |
+3.3v |
A43 |
PAR |
B44 |
-C/BE 1 |
A44 |
Address/Data 15 |
B45 |
Address/Data 14 |
A45 |
+3.3v |
B46 |
Ground |
A46 |
Address/Data 13 |
B47 |
Address/Data 12 |
A47 |
Address/Data 11 |
B48 |
Address/Data 10 |
A48 |
Ground |
B49 |
Ground / M66EN **** |
A49 |
Address/Data 9 |
B50 |
Access key |
A50 |
Access key |
B51 |
Access key |
A51 |
Access key |
B52 |
Address/Data 8 |
A52 |
-C/BE 0 |
B53 |
Address/Data 7 |
A53 |
+3.3v |
B54 |
+3.3v |
A54 |
Address/Data 6 |
B55 |
Address/Data 5 |
A55 |
Address/Data 4 |
B56 |
Address/Data 3 |
A56 |
Ground |
B57 |
Ground |
A57 |
Address/Data 2 |
B58 |
Address/Data 1 |
A58 |
Address/Data 0 |
B59 |
+v I/O |
A59 |
+v I/O |
B60 |
-ACK64 |
A60 |
-REQ64 |
B61 |
+5v |
A61 |
+5v |
B62 |
+5v |
A62 |
+5v |
|
Access key |
|
Access key |
B63 |
Reserved |
A63 |
Ground |
B64 |
Ground |
A64 |
-C/BE 7 |
B65 |
-C/BE 6 |
A65 |
-C/BE 5 |
B66 |
-C/BE 4 |
A66 |
+v I/O |
B67 |
Ground |
A67 |
PAR64 |
B68 |
Address/Data 63 |
A68 |
Address/Data 62 |
B69 |
Address/Data 61 |
A69 |
Ground |
B70 |
+v I/O |
A70 |
Address/Data 60 |
B71 |
Address/Data 59 |
A71 |
Address/Data 58 |
B72 |
Address/Data 57 |
A72 |
Ground |
B73 |
Ground |
A73 |
Address/Data 56 |
B74 |
Address/Data 55 |
A74 |
Address/Data 54 |
B75 |
Address/Data 53 |
A75 |
+v I/O |
B76 |
Ground |
A76 |
Address/Data 52 |
B77 |
Address/Data 51 |
A77 |
Address/Data 50 |
B78 |
Address/Data 49 |
A78 |
Ground |
B79 |
+v I/O |
A79 |
Address/Data 48 |
B80 |
Address/Data 47 |
A80 |
Address/Data 46 |
B81 |
Address/Data 45 |
A81 |
Ground |
B82 |
Ground |
A82 |
Address/Data 44 |
B83 |
Address/Data 43 |
A83 |
Address/Data 42 |
B84 |
Address/Data 41 |
A84 |
+v I/O |
B85 |
Ground |
A85 |
Address/Data 40 |
B86 |
Address/Data 39 |
A86 |
Address/Data 38 |
B87 |
Address/Data 37 |
A87 |
Ground |
B88 |
+v I/O |
A88 |
Address/Data 36 |
B89 |
Address/Data 35 |
A89 |
Address/Data 34 |
B90 |
Address/Data 33 |
A90 |
Ground |
B91 |
Ground |
A91 |
Address/Data 32 |
B92 |
Reserved |
A92 |
Reserved |
B93 |
Reserved |
A93 |
Ground |
B94 |
Ground |
A94 |
Reserved |
A = Back side, B = Component side
* In the PCI-X bus, pin B38 is defined as PCIXCAP. ** In the PCI 2.2 bus, pin A40 is Reserved. In the PCI 2.3 bus,
pin A40 is defined as SMBCLK (SM Bus Clock). *** In the PCI 2.2 bus, pin A41 is Reserved. In the PCI 2.3 bus, pin A41 is
defined as SMBDAT (SM Bus Data). **** In the PCI 2.1 bus, pin B49 is defined as the M66EN (66MHz enable) pin for 3.3v cards.
For 5v cards, pin B49 remains defined as Ground.
FIG. 5.15 The universal PCI slot and card configuration.
PCI-X
In September 1999, a new generation of the PCI bus was developed, called PCI-X. PCI-X can run at 133MHz, resulting in a
maximum data transfer rate of 1,066M/sec in 64-bit mode. Also a 100MHz and a 66MHz mode are defined. Look at the chart below
for an overview of the different modes.
Mode |
Clock Rate |
Transfer Rate (32-bit) |
Transfer Rate (64-bit) |
PCI-X 66 |
66MHz |
266M/sec |
533M/sec |
PCI-X 100 |
100MHz |
400M/sec |
800M/sec |
PCI-X 133 |
133MHz |
533M/sec |
1,066M/sec |
The PCI-X specification is fully backward-compatible with the conventional 3.3v PCI standard. It uses the same connector
and pinout. When a conventional (3.3v or universal) PCI card is installed in a PCI-X slot, the bus switches to conventional
mode. Also a PCI-X card switches to conventional mode when it is installed in a conventional PCI slot.
Another advantage of the PCI-X specification is the improved error handling. The cards have an increased range of options
for handling data parity errors and termination exceptions. Also the use of wait states is more intelligent. Only target initial
wait states are supported. No additional software initialisation is required, PCI-X is completely functional using the conventional
PCI-support of the BIOS, the device drivers and the operating system.
PCI-X uses pin B38 of the PCI connector to determine whether the device is capable of the higher PCI-X frequency.
PCI-X 2.0
In April 2002, version 2.0 of the PCI-X standard was released. PCI-X 2.0 introduces two new speed grades: PCI-X 266 (266MHz)
and PCI-X 533 (533MHz). The specification is completely backward-compatible with the conventional 3.3v PCI standard and the
PCI-X 1.0 standard. Also no additional software initialisation is required.
To achieve the higher frequencies of PCI-X 2.0, lower voltage signal swings were required. As a result, PCI-X 266 and PCI-X
533 require 1.5v signaling. However, to maintain compatibility with previous-generations of 3.3v PCI technologies, the I/O
buffers have been carefully designed to support both signal levels. To provide additional fault tolerance, the PCI-X 2.0 specification
includes ECC (Error Correcting Code). Single-bit errors are automatically corrected, while dual-bit errors are tagged
for retransmission. Look at the chart below for an overview of the different modes.
Mode |
Clock Rate |
Transfer Rate (32-bit) |
Transfer Rate (64-bit) |
PCI-X 266 |
266MHz |
1,066M/sec |
2,133M/sec |
PCI-X 533 |
533MHz |
2,133M/sec |
4,266M/sec |
The AGP Bus
In 1997, Intel developed a new type of local bus. AGP (Accelerated Graphics Port) is a 32-bit bus, specially for graphics
purposes, like video cards.
AGP is based on the PCI 2.1 standard which calls for a 66MHz bus speed. The peak bandwith of the AGP bus is four times
higher than the PCI 2.1 bus, resulting in a much smoother frame rate, and the ability to display 3D graphics with a much higher
quality. The maximum transfer rate of the slowest mode is 266M/sec with a clock rate of 66MHz. AGP attains this high transfer
rate due to it's ability to transfer data on both the rising and falling edges of the clock, and through new design advances
that have made data transfer modes more efficient.
DIME (DIrect Memory Execute) is one of the most important features of AGP. This technology allows the graphics chips to
access the main memory directly for the complex operation of texture mapping. Additionally, AGP doesn't share bandwith with
other devices, like PCI does.
AGP 2.0
The AGP 2.0 specification, which includes the original 1.0 version, provides for two faster modes of operation: 2x (called
AGP2X) and 4x (called AGP4X). The most important thing about the various modes is that they are all running at the AGP bus
speed of 66MHz. The difference is, an AGP2X graphics card sends data twice every clock cycle instead of once, and an AGP4X
card sends data four times per cycle.
The AGP specification defines three different expansion slot connectors: a 3.3v connector, a 1.5v connector and a universal
connector. All connectors are keyed to prevent plugging in incompatible cards. Table 5.10 shows the 3.3v AGP pinouts, and
Figure 5.16 shows the pin locations. Table 5.11 shows the 1.5v AGP pinouts; the pin locations are indicated in Figure 5.17.
Finally, Table 5.12 shows the pinouts, and Figure 5.18 shows the pin locations for a universal AGP slot and card. The pinouts
are based on the AGP 2.0 specification.
Table 5.10 Pinouts for a 3.3v AGP 2.0 Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
-OVRCNT |
A1 |
+12v |
B2 |
+5v |
A2 |
-TYPEDET * |
B3 |
+5v |
A3 |
Reserved |
B4 |
USB+ |
A4 |
USB- |
B5 |
Ground |
A5 |
Ground |
B6 |
-INT B |
A6 |
-INT A |
B7 |
CLK |
A7 |
-RST |
B8 |
-REQ |
A8 |
-GNT |
B9 |
+3.3v |
A9 |
+3.3v |
B10 |
ST0 |
A10 |
ST1 |
B11 |
ST2 |
A11 |
Reserved |
B12 |
-RBF |
A12 |
-PIPE |
B13 |
Ground |
A13 |
Ground |
B14 |
Reserved |
A14 |
Reserved |
B15 |
SBA 0 |
A15 |
SBA 1 |
B16 |
+3.3v |
A16 |
+3.3v |
B17 |
SBA 2 |
A17 |
SBA 3 |
B18 |
SB_STB |
A18 |
Reserved |
B19 |
Ground |
A19 |
Ground |
B20 |
SBA 4 |
A20 |
SBA 5 |
B21 |
SBA 6 |
A21 |
SBA 7 |
B22 |
Access key |
A22 |
Access key |
B23 |
Access key |
A23 |
Access key |
B24 |
Access key |
A24 |
Access key |
B25 |
Access key |
A25 |
Access key |
B26 |
Address/Data 31 |
A26 |
Address/Data 30 |
B27 |
Address/Data 29 |
A27 |
Address/Data 28 |
B28 |
+3.3v |
A28 |
+3.3v |
B29 |
Address/Data 27 |
A29 |
Address/Data 26 |
B30 |
Address/Data 25 |
A30 |
Address/Data 24 |
B31 |
Ground |
A31 |
Ground |
B32 |
AD_STB1 |
A32 |
Reserved |
B33 |
Address/Data 23 |
A33 |
-C/BE 3 |
B34 |
Vddq3.3 |
A34 |
Vddq3.3 |
B35 |
Address/Data 21 |
A35 |
Address/Data 22 |
B36 |
Address/Data 19 |
A36 |
Address/Data 20 |
B37 |
Ground |
A37 |
Ground |
B38 |
Address/Data 17 |
A38 |
Address/Data 18 |
B39 |
-C/BE 2 |
A39 |
Address/Data 16 |
B40 |
Vddq3.3 |
A40 |
Vddq3.3 |
B41 |
-IRDY |
A41 |
-FRAME |
B42 |
+3.3v AUX |
A42 |
Reserved |
B43 |
Ground |
A43 |
Ground |
B44 |
Reserved |
A44 |
Reserved |
B45 |
+3.3v |
A45 |
+3.3v |
B46 |
-DEVSEL |
A46 |
-TRDY |
B47 |
Vddq3.3 |
A47 |
-STOP |
B48 |
-PERR |
A48 |
-PME |
B49 |
Ground |
A49 |
Ground |
B50 |
SERR |
A50 |
PAR |
B51 |
C/BE 1 |
A51 |
Address/Data 15 |
B52 |
Vddq3.3 |
A52 |
Vddq3.3 |
B53 |
Address/Data 14 |
A53 |
Address/Data 13 |
B54 |
Address/Data 12 |
A54 |
Address/Data 11 |
B55 |
Ground |
A55 |
Ground |
B56 |
Address/Data 10 |
A56 |
Address/Data 9 |
B57 |
Address/Data 8 |
A57 |
C/BE 0 |
B58 |
Vddq3.3 |
A58 |
Vddq3.3 |
B59 |
AD_STB0 |
A59 |
Reserved |
B60 |
Address/Data 7 |
A60 |
Address/Data 6 |
B61 |
Ground |
A61 |
Ground |
B62 |
Address/Data 5 |
A62 |
Address/Data 4 |
B63 |
Address/Data 3 |
A63 |
Address/Data 2 |
B64 |
Vddq3.3 |
A64 |
Vddq3.3 |
B65 |
Address/Data 1 |
A65 |
Address/Data 0 |
B66 |
Reserved |
A66 |
Reserved |
A = Back side, B = Component side
* All 3.3v cards leave the TYPEDET signal open.
FIG. 5.16 The 3.3v AGP slot and card configuration.
Table 5.11 Pinouts for a 1.5v AGP 2.0 Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
-OVRCNT |
A1 |
+12v |
B2 |
+5v |
A2 |
-TYPEDET * |
B3 |
+5v |
A3 |
Reserved |
B4 |
USB+ |
A4 |
USB- |
B5 |
Ground |
A5 |
Ground |
B6 |
-INT B |
A6 |
-INT A |
B7 |
CLK |
A7 |
-RST |
B8 |
-REQ |
A8 |
-GNT |
B9 |
+3.3v |
A9 |
+3.3v |
B10 |
ST0 |
A10 |
ST1 |
B11 |
ST2 |
A11 |
Reserved |
B12 |
-RBF |
A12 |
-PIPE |
B13 |
Ground |
A13 |
Ground |
B14 |
Reserved |
A14 |
-WBF |
B15 |
SBA 0 |
A15 |
SBA 1 |
B16 |
+3.3v |
A16 |
+3.3v |
B17 |
SBA 2 |
A17 |
SBA 3 |
B18 |
SB_STB |
A18 |
-SB_STB |
B19 |
Ground |
A19 |
Ground |
B20 |
SBA 4 |
A20 |
SBA 5 |
B21 |
SBA 6 |
A21 |
SBA 7 |
B22 |
Reserved |
A22 |
Reserved |
B23 |
Ground |
A23 |
Ground |
B24 |
+3.3v AUX |
A24 |
Reserved |
B25 |
+3.3v |
A25 |
+3.3v |
B26 |
Address/Data 31 |
A26 |
Address/Data 30 |
B27 |
Address/Data 29 |
A27 |
Address/Data 28 |
B28 |
+3.3v |
A28 |
+3.3v |
B29 |
Address/Data 27 |
A29 |
Address/Data 26 |
B30 |
Address/Data 25 |
A30 |
Address/Data 24 |
B31 |
Ground |
A31 |
Ground |
B32 |
AD_STB1 |
A32 |
-AD_STB1 |
B33 |
Address/Data 23 |
A33 |
-C/BE 3 |
B34 |
Vddq1.5 |
A34 |
Vddq1.5 |
B35 |
Address/Data 21 |
A35 |
Address/Data 22 |
B36 |
Address/Data 19 |
A36 |
Address/Data 20 |
B37 |
Ground |
A37 |
Ground |
B38 |
Address/Data 17 |
A38 |
Address/Data 18 |
B39 |
-C/BE 2 |
A39 |
Address/Data 16 |
B40 |
Vddq1.5 |
A40 |
Vddq1.5 |
B41 |
-IRDY |
A41 |
-FRAME |
B42 |
Access key |
A42 |
Access key |
B43 |
Access key |
A43 |
Access key |
B44 |
Access key |
A44 |
Access key |
B45 |
Access key |
A45 |
Access key |
B46 |
-DEVSEL |
A46 |
-TRDY |
B47 |
Vddq1.5 |
A47 |
-STOP |
B48 |
-PERR |
A48 |
-PME |
B49 |
Ground |
A49 |
Ground |
B50 |
SERR |
A50 |
PAR |
B51 |
C/BE 1 |
A51 |
Address/Data 15 |
B52 |
Vddq1.5 |
A52 |
Vddq1.5 |
B53 |
Address/Data 14 |
A53 |
Address/Data 13 |
B54 |
Address/Data 12 |
A54 |
Address/Data 11 |
B55 |
Ground |
A55 |
Ground |
B56 |
Address/Data 10 |
A56 |
Address/Data 9 |
B57 |
Address/Data 8 |
A57 |
C/BE 0 |
B58 |
Vddq1.5 |
A58 |
Vddq1.5 |
B59 |
AD_STB0 |
A59 |
-AD_STB0 |
B60 |
Address/Data 7 |
A60 |
Address/Data 6 |
B61 |
Ground |
A61 |
Ground |
B62 |
Address/Data 5 |
A62 |
Address/Data 4 |
B63 |
Address/Data 3 |
A63 |
Address/Data 2 |
B64 |
Vddq1.5 |
A64 |
Vddq1.5 |
B65 |
Address/Data 1 |
A65 |
Address/Data 0 |
B66 |
Vrefcg |
A66 |
Vrefgc |
A = Back side, B = Component side
* All 1.5v cards connect the TYPEDET signal to Ground.
FIG. 5.17 The 1.5v AGP slot and card configuration.
Table 5.12 Pinouts for a Universal AGP 2.0 Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
-OVRCNT |
A1 |
+12v |
B2 |
+5v |
A2 |
-TYPEDET * |
B3 |
+5v |
A3 |
Reserved |
B4 |
USB+ |
A4 |
USB- |
B5 |
Ground |
A5 |
Ground |
B6 |
-INT B |
A6 |
-INT A |
B7 |
CLK |
A7 |
-RST |
B8 |
-REQ |
A8 |
-GNT |
B9 |
+3.3v |
A9 |
+3.3v |
B10 |
ST0 |
A10 |
ST1 |
B11 |
ST2 |
A11 |
Reserved |
B12 |
-RBF |
A12 |
-PIPE |
B13 |
Ground |
A13 |
Ground |
B14 |
Reserved |
A14 |
-WBF |
B15 |
SBA 0 |
A15 |
SBA 1 |
B16 |
+3.3v |
A16 |
+3.3v |
B17 |
SBA 2 |
A17 |
SBA 3 |
B18 |
SB_STB |
A18 |
-SB_STB |
B19 |
Ground |
A19 |
Ground |
B20 |
SBA 4 |
A20 |
SBA 5 |
B21 |
SBA 6 |
A21 |
SBA 7 |
B22 |
Reserved |
A22 |
Reserved |
B23 |
Ground |
A23 |
Ground |
B24 |
+3.3v AUX |
A24 |
Reserved |
B25 |
+3.3v |
A25 |
+3.3v |
B26 |
Address/Data 31 |
A26 |
Address/Data 30 |
B27 |
Address/Data 29 |
A27 |
Address/Data 28 |
B28 |
+3.3v |
A28 |
+3.3v |
B29 |
Address/Data 27 |
A29 |
Address/Data 26 |
B30 |
Address/Data 25 |
A30 |
Address/Data 24 |
B31 |
Ground |
A31 |
Ground |
B32 |
AD_STB1 |
A32 |
-AD_STB1 |
B33 |
Address/Data 23 |
A33 |
-C/BE 3 |
B34 |
Vddq |
A34 |
Vddq |
B35 |
Address/Data 21 |
A35 |
Address/Data 22 |
B36 |
Address/Data 19 |
A36 |
Address/Data 20 |
B37 |
Ground |
A37 |
Ground |
B38 |
Address/Data 17 |
A38 |
Address/Data 18 |
B39 |
-C/BE 2 |
A39 |
Address/Data 16 |
B40 |
Vddq |
A40 |
Vddq |
B41 |
-IRDY |
A41 |
-FRAME |
B42 |
+3.3v AUX |
A42 |
Reserved |
B43 |
Ground |
A43 |
Ground |
B44 |
Reserved |
A44 |
Reserved |
B45 |
+3.3v |
A45 |
+3.3v |
B46 |
-DEVSEL |
A46 |
-TRDY |
B47 |
Vddq |
A47 |
-STOP |
B48 |
-PERR |
A48 |
-PME |
B49 |
Ground |
A49 |
Ground |
B50 |
SERR |
A50 |
PAR |
B51 |
C/BE 1 |
A51 |
Address/Data 15 |
B52 |
Vddq |
A52 |
Vddq |
B53 |
Address/Data 14 |
A53 |
Address/Data 13 |
B54 |
Address/Data 12 |
A54 |
Address/Data 11 |
B55 |
Ground |
A55 |
Ground |
B56 |
Address/Data 10 |
A56 |
Address/Data 9 |
B57 |
Address/Data 8 |
A57 |
C/BE 0 |
B58 |
Vddq |
A58 |
Vddq |
B59 |
AD_STB0 |
A59 |
-AD_STB0 |
B60 |
Address/Data 7 |
A60 |
Address/Data 6 |
B61 |
Ground |
A61 |
Ground |
B62 |
Address/Data 5 |
A62 |
Address/Data 4 |
B63 |
Address/Data 3 |
A63 |
Address/Data 2 |
B64 |
Vddq |
A64 |
Vddq |
B65 |
Address/Data 1 |
A65 |
Address/Data 0 |
B66 |
Vrefcg |
A66 |
Vrefgc |
A = Back side, B = Component side
* All 3.3v cards leave the TYPEDET signal open, all 1.5v cards connect this signal to Ground.
FIG. 5.18 The universal AGP slot and card configuration.
AGP Pro
An extension of the AGP4X specification is AGP Pro. AGP Pro extends the existing AGP connectors on both ends to
deliver additional power on the 12v and 3.3v rails. AGP Pro is designed for professional-level video cards. Low power AGP
Pro cards that consume 25 to 50 watts of power are classified as AGP Pro50 cards. In addition, the AGP Pro standard
calls for at least one PCI slot to remain unoccupied adjacent to the AGP Pro50 card for cooling purposes. High power AGP Pro
cards that consume 50 to 110 watts of power are called AGP Pro110 cards. The standard requires at least two PCI slots
to remain unoccupied adjacent to the AGP Pro110 card for cooling purposes. A computer with either an AGP Pro slot will also
work with AGP1X, AGP2X and AGP4X cards. Table 5.13 shows the pinouts for the AGP Pro connectors, Figure 5.19 shows the location
of the connectors and the pins.
Table 5.13 Pinouts for the AGP Pro Connectors
Pin |
Signal Name |
Pin |
Signal Name |
D1 |
+3.3v |
C1 |
+3.3v |
D2 |
+3.3v |
C2 |
Ground |
D3 |
+3.3v |
C3 |
+3.3v |
D4 |
+3.3v |
C4 |
Ground |
D5 |
+3.3v |
C5 |
Ground |
D6 |
+3.3v |
C6 |
Ground |
D7 |
+3.3v |
C7 |
Ground |
D8 |
+3.3v |
C8 |
Ground |
D9 |
-PRSNT2 |
C9 |
Reserved |
D10 |
-PRSNT1 |
C10 |
Reserved |
|
Access key |
|
Access key |
B1...B66 |
- Standard AGP Connector - |
A1...A66 |
- Standard AGP Connector - |
|
Access key |
|
Access key |
F1 |
Reserved |
E1 |
Reserved |
F2 |
Reserved |
E2 |
Reserved |
F3 |
Ground |
E3 |
+12v |
F4 |
Ground |
E4 |
+12v |
F5 |
Ground |
E5 |
+12v |
F6 |
Ground |
E6 |
+12v |
F7 |
Ground |
E7 |
+12v |
F8 |
Ground |
E8 |
+12v |
F9 |
Ground |
E9 |
+12v |
F10 |
Ground |
E10 |
+12v |
F11 |
Ground |
E11 |
+12v |
F12 |
Ground |
E12 |
+12v |
F13 |
Ground |
E13 |
+12v |
F14 |
Ground |
E14 |
+12v |
C/E = Back side, D/F = Component side
FIG. 5.19 The AGP Pro connector configuration.
AGP 3.0
In August 2002, the AGP 3.0 specification was released. AGP 3.0 adds another mode of operation: 8x (called AGP8X). Although
it is based on the same 66MHz clock, the AGP8X specification is different in that features that were not being utilized, have
been removed in order to simplify and streamline the disign. Also other features have been added. The effective clock rate
is increased to 533MHz, resulting in a transfer rate of 2,133M/sec. The 3.3v specification is still supported, but considered
as obsolete. Table 5.14 shows the pinouts for the 1.5v AGP 3.0 bus.
Table 5.14 Pinouts for a 1.5v AGP 3.0 Bus
Pin |
Signal Name |
Pin |
Signal Name |
B1 |
-OVRCNT |
A1 |
+12v |
B2 |
+5v |
A2 |
-TYPEDET * |
B3 |
+5v |
A3 |
-GC_DET * |
B4 |
USB+ |
A4 |
USB- |
B5 |
Ground |
A5 |
Ground |
B6 |
-INT B |
A6 |
-INT A |
B7 |
CLK |
A7 |
-RST |
B8 |
-REQ |
A8 |
-GNT |
B9 |
+3.3v |
A9 |
+3.3v |
B10 |
ST0 |
A10 |
ST1 |
B11 |
ST2 |
A11 |
-MB_DET |
B12 |
RBF |
A12 |
DBI_HI |
B13 |
Ground |
A13 |
Ground |
B14 |
DBI_LO |
A14 |
WBF |
B15 |
-SBA 0 |
A15 |
-SBA 1 |
B16 |
+3.3v |
A16 |
+3.3v |
B17 |
-SBA 2 |
A17 |
-SBA 3 |
B18 |
SB_STBF |
A18 |
SB_STBS |
B19 |
Ground |
A19 |
Ground |
B20 |
-SBA 4 |
A20 |
-SBA 5 |
B21 |
-SBA 6 |
A21 |
-SBA 7 |
B22 |
Reserved |
A22 |
Reserved |
B23 |
Ground |
A23 |
Ground |
B24 |
+3.3v AUX |
A24 |
Reserved |
B25 |
+3.3v |
A25 |
+3.3v |
B26 |
Address/Data 31 |
A26 |
Address/Data 30 |
B27 |
Address/Data 29 |
A27 |
Address/Data 28 |
B28 |
+3.3v |
A28 |
+3.3v |
B29 |
Address/Data 27 |
A29 |
Address/Data 26 |
B30 |
Address/Data 25 |
A30 |
Address/Data 24 |
B31 |
Ground |
A31 |
Ground |
B32 |
AD_STBF1 |
A32 |
AD_STBS1 |
B33 |
Address/Data 23 |
A33 |
-C/BE 3 |
B34 |
Vddq1.5 |
A34 |
Vddq1.5 |
B35 |
Address/Data 21 |
A35 |
Address/Data 22 |
B36 |
Address/Data 19 |
A36 |
Address/Data 20 |
B37 |
Ground |
A37 |
Ground |
B38 |
Address/Data 17 |
A38 |
Address/Data 18 |
B39 |
-C/BE 2 |
A39 |
Address/Data 16 |
B40 |
Vddq1.5 |
A40 |
Vddq1.5 |
B41 |
IRDY |
A41 |
FRAME |
B42 |
Access key |
A42 |
Access key |
B43 |
Access key |
A43 |
Access key |
B44 |
Access key |
A44 |
Access key |
B45 |
Access key |
A45 |
Access key |
B46 |
DEVSEL |
A46 |
TRDY |
B47 |
Vddq1.5 |
A47 |
STOP |
B48 |
PERR |
A48 |
-PME |
B49 |
Ground |
A49 |
Ground |
B50 |
SERR |
A50 |
PAR |
B51 |
-C/BE 1 |
A51 |
Address/Data 15 |
B52 |
Vddq1.5 |
A52 |
Vddq1.5 |
B53 |
Address/Data 14 |
A53 |
Address/Data 13 |
B54 |
Address/Data 12 |
A54 |
Address/Data 11 |
B55 |
Ground |
A55 |
Ground |
B56 |
Address/Data 10 |
A56 |
Address/Data 9 |
B57 |
Address/Data 8 |
A57 |
-C/BE 0 |
B58 |
Vddq1.5 |
A58 |
Vddq1.5 |
B59 |
AD_STBF0 |
A59 |
AD_STBS0 |
B60 |
Address/Data 7 |
A60 |
Address/Data 6 |
B61 |
Ground |
A61 |
Ground |
B62 |
Address/Data 5 |
A62 |
Address/Data 4 |
B63 |
Address/Data 3 |
A63 |
Address/Data 2 |
B64 |
Vddq1.5 |
A64 |
Vddq1.5 |
B65 |
Address/Data 1 |
A65 |
Address/Data 0 |
B66 |
Vrefcg |
A66 |
Vrefgc |
A = Back side, B = Component side
* All 1.5v cards connect the -TYPEDET and the -GC_DET signal to Ground.
As you can see in the pinout table, in the AGP 3.0 specification a few additional signals have been defined to take the
place of previously reserved pins. Furthermore, the polarity of certain signals is different from AGP 2.0.
Look at Table 5.15 to see how all of the AGP modes compare.
Table 5.15 Overview of the Different AGP Modes
Mode |
AGP Version |
Effective Clock Rate |
Transfer Rate |
Maximum Power |
AGP (AGP1X) |
1.0 |
66MHz |
266M/sec |
25 watts |
AGP2X |
2.0 |
133MHz |
533M/sec |
25 watts |
AGP4X |
2.0 |
266MHz |
1,066M/sec |
25 watts |
AGP Pro50 |
2.0 |
266MHz |
1,066M/sec |
50 watts * |
AGP Pro110 |
2.0 |
266MHz |
1,066M/sec |
110 watts * |
AGP8X |
3.0 |
533MHz |
2,133M/sec |
25 watts |
* AGP Pro uses an extended connector. When using an AGP Pro50 card, at least one PCI slot must remain unused adjacent
to the AGP Pro50 card for cooling purposes. When using an AGP Pro110 card, at least two PCI slots must remain unused.
The AGP2X, AGP4X and AGP8X standards are backward-compatible. For example, a computer with an AGP8X slot will also work
with AGP1X, AGP2X and AGP4X cards. But an AGP1X slot is not compatible with either of the other specifications.
USB
The Universal Serial Bus (USB) is also a newer bus technology with high capabilities. The first USB specification
was published in September 1995 by a consortium comprised of representatives from Compaq, Digital, IBM, Intel, Microsoft,
NEC, and Northern Telecom. In 1996, revision 1.1 was published.
Another benefit of the USB specification is self-identifying peripherals, a feature that should greatly ease installations.
This feature is fully compatible with Plug and Play systems and provides an industry standard for future connectivity. Also,
USB devices can be "hot" plugged or unplugged, meaning that you should not have to turn off your computer every time you want
to connect or disconnect a peripheral. One thing to keep in mind before using USB peripherals is that your operating system
must offer USB support. Whereas the original Windows 95 upgrade and NT 4.0 do not support USB, the later OSR-2 (OEM Service
Release 2) release of Windows 95 does. Newer versions of Windows do fully support USB.
The USB is a 12Mbit/sec (1.5M/sec) interface over a simple four-wire connection (one twisted pair of clock and data lines
plus two power lines). Along with the signal USB carries a 5v, 0.5 amps power supply to drive small devices. For low-performance
peripherals such as pointing devices and keyboards, the USB also has a slower 1.5Mbit/sec subchannel.
The bus supports up to 127 devices and uses a tiered star topology built on expansion hubs that can reside in the PC, any
USB peripheral, or even stand-alone hub boxes. Devices can be connected by daisy-chaining, or by using a USB hub which itself
has a number of USB sockets and plugs into a PC or other device. 7 peripherals can be attached to each hub device. This can
include a second hub to which up to another 7 peripherals can be connected, and so on. Each cable between devices is limited
to a length of 5 meters (3 meters when an unshielded cable is used). Figure 5.20 shows the shielded USB cable.
FIG. 5.20 The shielded USB cable.
Devices are plugged directly into a four-pin socket on the PC or hub using a rectangular Type A socket. All cables that
are permanently attached to the device have a Type A plug. Devices that use a separate cable have a square Type B socket,
and the cable that connects them has a Type A and Type B plug. Figure 5.21 shows the two types of USB connectors.
FIG. 5.21 USB connector Type A and Type B.
USB 2.0
In 2001, USB version 2.0 was released. USB 2.0 has a maximum data transfer rate of 480Mbit/sec (60M/sec). USB 2.0 is backward-compatible
with USB 1.1 and uses the same types of connectors.
FireWire (IEEE 1394)
IEEE 1394 (also called FireWire) is a high-speed local serial bus, published by the IEEE Standards Board
in late 1995. IEEE 1394 supports speeds of 100, 200, and 400Mbit/sec (12.5, 25, and 50M/sec). This bus was derived from the
"FireWire" bus originally developed by Apple and Texas Instruments, and is also a part of the newer Serial SCSI standard.
IEEE 1394 is fully Plug and Play, including the ability for hot plugging (insertion and removal of components without powering
down). Unlike the much more complicated parallel SCSI bus, IEEE 1394 does not require complicated termination, and devices
connected to the bus can draw up to 1.5 amps of electrical power.
IEEE 1394 is built on a daisy-chained and branched topology and allows up to 63 nodes with a chain of up to 16 devices
on each node. If this is not enough, the standard also calls for up to 1,023 bridged buses, which can interconnect more than
64,000 nodes! Additionally, IEEE 1394 can support devices with different data rates on the same bus, just as with SCSI.
Also an important element of FireWire is the support of isochronous devices. In isochronous mode, data streams between
the device and the host in real-time, with guaranteed bandwidth and no error correction. Essentially, this means that a device
like a digital camcorder can request that the host computer allocate enough bandwith for the camcorder to send uncompressed
video in real-time to the computer. When the FireWire connection enters isochronous mode, the camera can send the video in
a steady flow to the computer, without anything disrupting the process.
FireWire uses 64-bit fixed addressing, based on the IEEE 1212 standard. There are three parts to each packet of information
sent by a device over FireWire:
- A 10-bit Bus ID that is used to determine which FireWire bus the data came from
- A 6-bit Physical ID that identifies which device on the bus sent the data
- A 48-bit Storage Area that is capable of addressing 256 Terabytes of information for each node
IEEE 1394 uses a simple six-wire cable with two differential pairs of clock and data lines plus two power lines. Individual
FireWire cables can run as long as 4.5 meters. Data can send through up to 16 hops for a total maximum distance of 72 meters.
Hops occur when devices are daisy-chained together. Figure 5.22 shows the FireWire cable, while Figure 5.23 shows the FireWire
connector.
FIG. 5.22 The FireWire cable.
FIG. 5.23 The FireWire connector.
The types of devices that are connected to the PC via IEEE 1394 include practically anything that might be using SCSI otherwise.
This includes all forms of disk drives, including hard disk, optical, floppy, CD-ROM, and DVD (Digital Versatile Disc) drives.
Also digital cameras, tape drives, and many other high-speed peripherals featuring IEEE 1394 interfaces built in.
System Resources
System resources are the communications channels, addresses, and other signals used by hardware devices to communicate
on the bus. At their lowest level, these resources typically include the following:
- Memory addresses
- IRQ (Interrupt ReQuest) channels
- DMA (Direct Memory Access) channels
- I/O Port addresses
These are listed roughly in the order you would experience problems with them. Memory conflicts are perhaps the most troublesome
of these, certainly the most difficult to fully explain and overcome. These are discussed in Chapter 7 - Memory, which focuses
on the others listed here in the order you will likely have problems with them. IRQs cause more problems than DMA because
they are in much higher demand; therefore, virtually all cards will use IRQ channels. There are fewer problems with DMA channels
because few cards use them, and there are usually more than enough channels to go around. I/O ports are used by all hardware
devices on the bus, but there are technically 64K of them, which means plenty to go around. With all of these resources, you
have to make sure that a unique card or hardware function uses each resource; they cannot or should not be shared.
These resources are required and used by many different components of your system. Adapter cards need these resources to
communicate with your system and to accomplish their purposes. Not all adapter cards have the same resource requirements.
A serial communications port, for example, needs an IRQ channel and I/O port address, whereas a sound board needs these resources
and at least one DMA channel as well. Most network cards use a 16K block of memory addresses, an IRQ channel, and an I/O port
address.
As your system increases in complexity, the chance for resource conflicts increases dramatically. Systems with sound cards
and network cards can really push the envelope and can become a configuration nightmare for the uninitiated. So that you can
resolve conflicts, most adapter cards allow you to modify resource assignments by setting jumpers or switches on the cards,
or running a software program to change the settings. Fortunately, in almost all cases there is a logical way to configure
the system--once you know the rules.
Interrupts (IRQs)
Interrupt request channels (IRQs), or hardware interrupts, are used by various hardware devices to signal the motherboard
that a request must be fulfilled. This procedure is the same as a student raising his hand to indicate that he needs attention.
These interrupt channels are represented by wires on the motherboard and in the slot connectors. When a particular interrupt
is invoked, a special routine takes over the system, which first saves all the CPU register contents in a stack and then directs
the system to the interrupt vector table. This vector table contains a list of memory addresses that correspond to the interrupt
channels. Depending on which interrupt was invoked, the program corresponding to that channel is run.
The pointers in the vector table point to the address of whatever software driver is used to service the card that generated
the interrupt. For a network card, for example, the vector may point to the address of the network drivers that have been
loaded to operate the card; for a hard disk controller, the vector may point to the BIOS code that operates the controller.
After the particular software routine finishes performing whatever function the card needed, the interrupt-control software
returns the stack contents to the CPU registers, and the system then resumes whatever it was doing before the interrupt occurred.
Through the use of interrupts, your system can respond to external events in a timely fashion. Each time that a serial
port presents a byte to your system, an interrupt is generated to ensure that the system reads that byte before another comes
in. Keep in mind that in some cases a port device--in particular, a modem with a 16550 or higher UART chip--may incorporate
a byte buffer that allows multiple characters to be stored before an interrupt is generated.
Hardware interrupts are generally prioritized by their numbers; with some exceptions, the highest-priority interrupts have
the lowest numbers. Higher-priority interrupts take precedence over lower-priority interrupts by interrupting them. As a result,
several interrupts can occur in your system concurrently, each interrupt nesting within another.
If you overload the system--in this case, by running out of stack resources (too many interrupts were generated too quickly)--an
internal stack overflow error occurs and your system halts. If you experience this type of system error and run DOS, you can
compensate for it by using the STACKS parameter in your CONFIG.SYS file to increase the available stack resources. Most people
will not see this error in Windows 95, Windows NT or later versions.
The ISA bus uses edge-triggered interrupt sensing, in which an interrupt is sensed by a signal sent on a particular
wire located in the slot connector. A different wire corresponds to each possible hardware interrupt. Because the motherboard
cannot recognize which slot contains the card that used an interrupt line and therefore generated the interrupt, confusion
would result if more than one card were set to use a particular interrupt. Each interrupt, therefore, usually is designated
for a single hardware device, and most of the time, interrupts cannot be shared.
A device can be designed to share interrupts, and a few devices allow this; most cannot, however, because of the way interrupts
are signaled in the ISA bus. Systems with the MCA bus use level-sensitive interrupts, which allow complete interrupt sharing
to occur. In fact, in an MCA system, all boards can be set to the same interrupt with no conflicts or problems. The EISA bus
can optionally use level-sensitive interrupts which allow sharing, but only for true EISA cards. For maximum performance,
however, interrupts should be staggered as much as possible.
External hardware interrupts often are referred to as maskable interrupts, which simply means that the interrupts
can be masked or turned off for a short time while the CPU is used for other critical operations. It is up to the programmer
to manage interrupts properly and efficiently for the best system performance.
Because interrupts usually cannot be shared in an ISA bus system, you often run into conflicts and can even run out of
interrupts when you are adding boards to a system. If two boards use the same IRQ to signal the system, the resulting conflict
prevents either board from operating properly. The following sections discuss the IRQs that any standard devices use, as well
as what may be free in your system.
8-Bit ISA Bus Interrupts
The PC and XT (the systems based on the 8-bit 8086 CPU) provide for eight different external hardware interrupts. Table
5.16 shows the typical uses for these interrupts, which are numbered 0 through 7.
Table 5.16 8-Bit ISA Bus Default Interrupt Assignments
IRQ |
Function |
Bus Slot |
0 |
System Timer |
No |
1 |
Keyboard Controller |
No |
2 |
Available |
Yes (8-bit) |
3 |
Serial Port 2 (COM2:) |
Yes (8-bit) |
4 |
Serial Port 1 (COM1:) |
Yes (8-bit) |
5 |
Hard Disk Controller |
Yes (8-bit) |
6 |
Floppy Disk Controller |
Yes (8-bit) |
7 |
Parallel Port 1 (LPT1:) |
Yes (8-bit) |
If you have a system that has one of the original 8-bit ISA buses, you will find that the IRQ resources provided by the
system present a severe limitation. Installing several devices that need the services of system IRQs in a PC/XT-type system
can be a study in frustration, because the only way to resolve the interrupt-shortage problem is to remove the adapter board
that you need the least.
16-Bit ISA, EISA, and MCA Bus Interrupts
The introduction of the AT, based on the 286 processor, was accompanied by an increase in the number of external hardware
interrupts that the bus would support. The number of interrupts was doubled to 16 by using two Intel 8259 interrupt controllers,
piping the interrupts generated by the second one through the unused IRQ 2 in the first controller. This arrangement effectively
means that only 15 IRQ assignments are available, and IRQ 2 effectively became inaccessible.
By routing all of the interrupts from the second IRQ controller through IRQ 2 on the first, all of these new interrupts
are assigned a nested priority level between IRQ 1 and IRQ 3. Thus, IRQ 15 ends up having a higher priority than IRQ 3. Figure
5.24 shows how the two 8259 chips were wired to create the cascade through IRQ 2 on the first chip.
FIG. 5.24 Interrupt controller cascade wiring.
To prevent problems with boards set to use IRQ 2, the AT system designers routed one of the new interrupts (IRQ 9) to fill
the slot position left open after removing IRQ 2. This means that any card you install in a system that claims to use IRQ
2 is really using IRQ 9 instead. Some cards now label this selection as IRQ 2/9, while others may only call it IRQ 2 or IRQ
9. No matter what the labeling says, you must never set two cards to use that interrupt!
Table 5.17 shows the typical uses for interrupts in the 16-bit ISA, EISA, and MCA buses, and lists them in priority order
from highest to lowest.
Table 5.17 16-Bit ISA, EISA, and MCA Default Interrupt Assignments
IRQ |
Standard Function |
Bus Slot |
Card Type |
0 |
System Timer |
No |
- |
1 |
Keyboard Controller |
No |
- |
2 |
2nd IRQ Controller Cascade |
No |
- |
3 |
Serial Port 2 (COM2:) |
Yes |
8/16-bit |
4 |
Serial Port 1 (COM1:) |
Yes |
8/16-bit |
5 |
Sound/Parallel Port 2 (LPT2:) |
Yes |
8/16-bit |
6 |
Floppy Disk Controller |
Yes |
8/16-bit |
7 |
Parallel Port 1 (LPT1:) |
Yes |
8/16-bit |
8 |
Real-Time Clock |
No |
- |
9 |
Network/Available (appears
as IRQ 2) |
Yes |
8/16-bit |
10 |
Available |
Yes |
16-bit |
11 |
SCSI/Available |
Yes |
16-bit |
12 |
Motherboard Mouse Port/Available |
Yes |
16-bit |
13 |
Math Coprocessor |
No |
- |
14 |
Primary IDE |
Yes |
16-bit |
15 |
Secondary IDE/Available |
Yes |
16-bit |
Because IRQ 2 now is used directly by the motherboard, the wire for IRQ 9 has been re-routed to the same position in the
slot that IRQ 2 normally would occupy. Therefore, any board you install that is set to IRQ 2 actually is using IRQ 9. The
interrupt vector table has been adjusted accordingly to enable this deception to work. This adjustment to the system provides
greater compatibility with the PC interrupt structure and enables cards that are set to IRQ 2 to work properly.
Notice that interrupts 0, 1, 2, 8, and 13 are not on the bus connectors and are not accessible to adapter cards. Interrupts
8, 10, 11, 12, 13, 14, and 15 are from the second interrupt controller and are accessible only by boards that use the 16-bit
extension connector, because this is where these wires are located. IRQ 9 is rewired to the 8-bit slot connector in place
of IRQ 2, which means that IRQ 9 replaces IRQ 2 and therefore is available to 8-bit cards, which treat it as though it were
IRQ 2.
NOTE: Although the 16-bit ISA bus has twice as many interrupts as systems that have the
8-bit ISA bus, you still may run out of available interrupts, because only 16-bit adapters can use most of the newly available
interrupts.
The extra IRQ lines in a 16-bit ISA system are of little help unless the adapter boards that you plan to use enable you
to configure them for one of the unused IRQs. Some devices are hard-wired so that they can use only a particular IRQ. If you
have a device that already uses that IRQ, you must resolve the conflict before installing the second adapter. If neither adapter
enables you to reconfigure its IRQ use, chances are that you cannot use the two devices in the same system.
IRQ Conflicts
One of the most common areas of IRQ conflict involves serial (COM) ports. You may have noticed in the preceding two sections
that two IRQs are set aside for two COM ports. IRQ 3 is used for COM2:, and IRQ 4 is used for COM1:. The problem occurs when
you have more than two serial ports in a system--a situation that is entirely possible, because a PC can support up to four
COM ports.
The problems arise here because most people purchase poorly designed COM port boards that do not allow IRQ settings other
than 3 or 4. What happens is that they end up setting COM3: to IRQ 4 (sharing it with COM1:), and COM4: to IRQ 3 (sharing
it with COM2:). This is not acceptable, as it will prevent you from using the two COM ports on any one of the interrupt channels
simultaneously. This was somewhat acceptable under plain DOS, because single-tasking (running only one program at a time)
was the order of the day, but is totally unacceptable with Windows and OS/2. If you must share IRQs, you can usually get away
with sharing devices on the same IRQ as long as they use different COM ports. For instance, a scanner and an internal modem
could share an IRQ, although if the two devices are used simultaneously a conflict will result.
The best solution is to purchase a multiport serial I/O card that will allow interrupt sharing among COM ports. As a side
note, also make sure that the COM board you purchase uses a buffered 16550A or higher type UART (Universal Asynchronous Receiver
Transmitter) chip rather than the slow, unbuffered 16450 types. One company providing specialized high quality COM boards
is Byte Runner Technologies.
If a device listed in the table is not present, such as the motherboard mouse port (IRQ 12) or parallel port 2 (IRQ 5),
then you can consider those interrupts as available. For example, a second parallel port is a rarity, and most systems will
have a sound card installed and set for IRQ 5. Also, on most systems IRQ 15 is assigned to a secondary IDE controller. If
you do not have a second IDE hard drive, you could disable the secondary IDE controller to free up that IRQ for another device.
DMA Channels
DMA (Direct Memory Access) channels are used by high-speed communications devices that must send and receive information
at high speed. A serial or parallel port does not use a DMA channel, but a sound card or SCSI adapter often does. DMA channels
sometimes can be shared if the devices are not of the type that would need them simultaneously. For example, you can have
a network adapter and a tape backup adapter sharing DMA channel 1, but you cannot back up while the network is running. To
back up during network operation, you must ensure that each adapter uses a unique DMA channel.
8-Bit ISA Bus DMA Channels
In the 8-bit ISA bus, four DMA channels support high-speed data transfers between I/O devices and memory. Three of the
channels are available to the expansion slots. Table 5.18 shows the typical uses of these DMA channels.
Table 5.18 8-Bit ISA Default DMA-Channel Assignments
DMA |
Standard Function |
Bus Slot |
0 |
Dynamic RAM Refresh |
No |
1 |
Available |
Yes (8-bit) |
2 |
Floppy disk controller |
Yes (8-bit) |
3 |
Hard disk controller |
Yes (8-bit) |
Because most systems typically have both a floppy and hard disk drive, only one DMA channel is available in 8-bit ISA systems.
16-Bit ISA DMA Channels
Since the introduction of the 286 CPU, the ISA bus has supported eight DMA channels, with seven channels available to the
expansion slots. Like the expanded IRQ lines described earlier in this chapter, the added DMA channels were created by cascading
a second DMA controller to the first one. DMA channel 4 is used to cascade channels 0 through 3 to the microprocessor. Channels
0 through 3 are available for 8-bit transfers, and channels 5 through 7 are for 16-bit transfers only. Table 5.19 shows the
typical uses for the DMA channels.
Table 5.19 16-Bit ISA, EISA, and MCA Default DMA-Channel Assignments
DMA |
Standard Function |
Bus Slot |
Card Type |
Transfer |
0 |
Available |
Yes |
16-bit |
8-bit |
1 |
Sound/Available |
Yes |
8/16-bit |
8-bit |
2 |
Floppy Disk Controller |
Yes |
8/16-bit |
8-bit |
3 |
ECP Parallel/Available |
Yes |
8/16-bit |
8-bit |
4 |
1st DMA Controller |
No |
- |
16-bit Cascade |
5 |
Sound/Available |
Yes |
16-bit |
16-bit |
6 |
SCSI/Available |
Yes |
16-bit |
16-bit |
7 |
Available |
Yes |
16-bit |
16-bit |
The only standard DMA channel used in all systems is DMA 2, which is universally used by the floppy controller. DMA 4 is
not usable, and does not appear in the bus slots. DMA channels 1 and 5 are most commonly used by sound cards such as the Sound
Blaster 16. These cards use both an 8- and a 16-bit DMA channel for high-speed transfers.
NOTE: Although DMA channel 0 appears in a 16-bit slot connector extension and therefore
can only be used by a 16-bit card, it only does 8-bit transfers! Because of this, you will generally not see DMA 0 as a choice
on 16-bit cards. Most 16-bit cards (like SCSI host adapters) that use DMA channels have their choices limited to DMA 5 through
7.
EISA
Realizing the shortcomings inherent in the way DMA channels are implemented in the ISA bus, the creators of the EISA specification
created a specific DMA controller for their new bus. They increased the number of address lines to include the entire address
bus, thus allowing transfers anywhere within the address space of the system. Each DMA channel can be set to run either 8-,
16-, or 32-bit transfers. In addition, each DMA channel can be separately programmed to run any of four types of bus cycles
when transferring data:
- Compatible. This transfer method is included to match the same DMA timing as used in the ISA bus. This is done
for compatibility reasons; all ISA cards can operate in an EISA system in this transfer mode.
- Type A. This transfer type compresses the DMA timing by 25 percent over the Compatible method. It was designed
to run with most (but not all) ISA cards and still yield a speed increase.
- Type B. This transfer type compresses timing by 50 percent over the Compatible method. Using this method, most
EISA cards function properly, but only a few ISA cards will be problem-free.
- Type C. This transfer method compresses timing by 87.5 percent over the Compatible method; it is the fastest DMA
transfer method available under the EISA specification. No ISA cards will work using this transfer method.
EISA DMA also allows for special reading and writing operations referred to as scatter write and gather read.
Scattered writes are done by reading a contiguous block of data and writing it to more than one area of memory at the same
time. Gathered reads involve reading from more than one place in memory and writing to a device. These functions are often
referred to as Buffered Chaining, and they increase the throughput of DMA operations.
MCA
It might be assumed that because MCA is a complete rebuilding of the PC bus structure that DMA in an MCA environment would
be better constructed. This is not so. Quite to the contrary, DMA in MCA systems were for the most part all designed around
one DMA controller with the following issues:
- It can only connect to two 8-bit data paths. This can only transfer 1 or 2 bytes per bus cycle.
- It is only connected to AO:A23 on the address bus. This means it can only make use of the lower 16M of memory.
- It runs at 10MHz.
The inability of the DMA controller to address more than 2 bytes per transfer severely cripples this otherwise powerful
bus.
I/O Port Addresses
Your computer's I/O ports enable you to attach a large number of important devices to your system to expand its capabilities.
A printer attached to one of your system's LPT (parallel) ports enables you to make a printout of the work on your system.
A modem attached to one of your system's COM (serial) ports enables you to use telephone lines to communicate with computers
thousands of miles away. A scanner attached to an LPT port or a SCSI host adapter enables you to convert graphics or text
to images and type that you can use with the software installed on your computer.
Most systems come configured with at least two COM (serial) ports and one LPT (parallel printer) ports. The two serial
ports are configured as COM1: and COM2:, and the parallel port as LPT1. The basic architecture of the PC provides for as many
as four COM ports (1 through 4) and three LPT ports (1 through 3). If you use more than two COM ports, make sure that COM3:
and COM4: have unique IRQ settings and do not share those with COM1: and COM2:. In general, on most machines both COM1: and
COM3: use IRQ 4; and both COM2: and COM4: use IRQ 3.
CAUTION: Theoretically, each of the four COM ports in a system can be used to attach a device,
such as a mouse or modem, but doing so may lead to resource conflicts. For more information, see the discussion of resolving
IRQ conflicts in "IRQ Conflicts" earlier in this chapter.
Every I/O port in your system uses an I/O address for communication. This address, which is in the lower memory ranges,
is reserved for communication between the I/O device and the operating system. If your system has multiple I/O cards, each
card must use a different I/O address; if not, your system will not be able to communicate with the devices reliably.
The I/O addresses that your ports use depend on the type of ports. Table 5.20 shows the I/O addresses expected by the various
standard ports in a PC system.
Table 5.20 Standard I/O Addresses for Serial and Parallel Ports
Port |
Base I/O Address |
COM1 |
3F8h |
COM2 |
2F8h |
COM3 |
3E8h |
COM4 |
2E8h |
LPT1 |
378h |
LPT2 |
278h |
Besides your serial and parallel ports, other adapters in your system use I/O addresses. Quite truthfully, the I/O addresses
for the serial and parallel ports are fairly standard; it is unlikely that you will run into problems with them. The I/O addresses
used by other adapters are not standardized, however, and you may have problems finding a mix of port addresses that works
reliably. In the next section, you learn some of the techniques that you can use to solve this problem.
Resolving Resource Conflicts
The resources in a system are limited. Unfortunately, the demands on those resources seem to be unlimited. As you add more
and more adapter cards to your system, you will find that the potential for resource conflicts increases. If your system is
fully PnP-compatible, then potential conflicts should be resolved automatically. If your system does not have a bus that resolves
conflicts for you (such as an MCA or EISA bus), you need to resolve the conflicts manually.
How do you know whether you have a resource conflict? Typically, one of the devices in your system stops working. Resource
conflicts can exhibit themselves in other ways, though. Any of the following events could be diagnosed as a resource conflict:
- A device transfers data inaccurately.
- Your system frequently locks up.
- Your sound card doesn't sound quite right.
- Your mouse doesn't work.
- Garbage appears on your video screen for no apparent reason.
- Your printer prints gibberish.
- You cannot format a floppy disk.
- The PC starts in Safe Mode (Windows 95).
In the following sections, you learn some of the steps that you can take to head off resource conflicts or to track them
down when they occur.
CAUTION: Be careful in diagnosing resource conflicts; a problem may not be a resource conflict
at all, but a computer virus. Many computer viruses are designed to exhibit themselves as glitches or as periodic problems.
If you suspect a resource conflict, it may be worthwhile to run a virus check first to ensure that the system is clean. This
procedure could save you hours of work and frustration.
Resolving Conflicts Manually
Unfortunately, the only way to resolve conflicts manually is to take the cover off your system and start changing switches
or jumper settings on your adapter cards. Each of these changes then must be accompanied by a system reboot, which implies
that they take a great deal of time. This situation brings us to the first rule of resolving conflicts: When you set about
ridding your system of resource conflicts, make sure that you allow a good deal of uninterrupted time.
Also make sure that you write down your current system settings before you start making changes. That way, you will know
where you began and can go back to the original configuration (if necessary).
Finally, dig out the manuals for all your adapter boards; you will need them. If you cannot find the manuals, contact the
manufacturers to determine what the various jumper positions and switch settings mean. Additionally, you could look for more
current information online at the manufacturers' Web sites.
Now you are ready to begin your detective work. As you try various switch settings and jumper positions, keep the following
questions in mind; the answers will help you narrow down the conflict areas:
- When did the conflict first become apparent? If the conflict occurred after you installed a new adapter card, that
new card probably is causing the conflict. If the conflict occurred after you started using new software, chances are good
that the software uses a device that is taxing your system's resources in a new way.
- Are there two similar devices in your system that do not work? For example, if your modem and mouse--devices that
use a COM port--do not work, chances are good that these devices are conflicting with each other.
- Have other people had the same problem, and if so, how did they resolve it? Public forums--such as Internet newsgroups--are
great places to find other users who may be able to help you solve the conflict.
Whenever you make changes in your system, reboot and see whether the problem persists. When you believe that you have solved
the problem, make sure that you test all your software. Fixing one problem often seems to causes another to crop up. The only
way to make sure that all problems are resolved is to test everything in your system.
As you attempt to resolve your resource conflicts, you should work with and update a system-configuration template, as
discussed in the following section.
Using a System-Configuration Template
A system-configuration template is helpful, simply because it is easier to remember something that is written down
than it is to keep it in your head. To create a configuration template, all you need to do is start writing down what resources
are used by which parts of your system. Then, when you need to make a change or add an adapter, you can quickly determine
where conflicts may arise.
You can use a worksheet split into three main areas--one for interrupts, another for DMA channels, and a middle area for
devices that do not use interrupts. Each section lists the IRQ or DMA channel on the left and the I/O port device range on
the right. This way, you get the clearest picture of what resources are used and which ones are available in a given system.
Here is the system-configuration template which is developed over the years. This type of configuration sheet is resource-based
instead of component-based. Each row in the template represents a different resource, and lists the component using the resource
as well as the resources used. The chart has pre-entered all of the fixed items in a PC, whose configuration cannot be changed.
To fill out this type of chart, you would perform the following steps:
- 1. Enter the default resources used by standard components, such as serial and parallel ports, disk controllers,
and video. You can use the filled out example to see how most standard devices are configured.
2. Enter the default resources used by additional add-on components such as sound cards, SCSI cards, network cards,
proprietary cards, and so on.
3. Change any configuration items that are in conflict. Try to leave built-in devices at their default settings,
as well as sound cards. Other installed adapters may have their settings changed, but be sure to document the changes.
Of course a template like this is best used when first installing components, not after. Once you have it completely filled
out to match your system, you can label it and keep it with the system. When you add any more devices, the template will be
your guide as to how any new devices should be configured.
The following example is the same template filled out for a typical PC system:
Form A: System Resource Worksheet Example A
Form B: System Resource Worksheet Example B
As you can see from this template, only two IRQs and two DMA channels remain available. In this example configuration,
the primary and secondary IDE connectors, the floppy controller, two serial ports and one parallel port were built into the
motherboard.
Whether the devices are built into the motherboard or on a separate card makes no difference because the resource allocations
are the same in either case. All default settings are normally used for these devices, and are indicated in the completed
configuration. Next, the accessory cards were configured. In this example, the following cards were installed:
- SVGA video card (ATI Mach 64)
- Sound card (Creative Labs Sound Blaster 16)
- SCSI host adapter (Adaptec AHA-1542CF)
- Network interface card (SMC EtherEZ)
It helps to install the cards in this order. Start with the video card; next, add the sound card. Due to problems with
software that must be configured to the sound card, it is best to install it early and make sure only default settings are
used. It is better to change settings on other cards than the sound card.
After the sound card, the SCSI adapter was installed; however, the default I/O Port addresses (330-331) and DMA channel
(DMA 5) used were in conflict with other cards (mainly the sound card). These settings were changed to their next logical
settings which did not cause a conflict.
Finally, the network card was installed, which also had default settings that conflicted with other cards. In this case,
the Ethernet card came pre-configured to IRQ 3, which was already in use by COM2:. The solution was to change the setting,
and IRQ 9 was the next logical choice in the card's configuration settings.
Even though this is a fully loaded configuration, only three individual items among all of the cards had to be changed
to achieve an optimum system configuration. As you can see, using a configuration template like the one shown can make what
would otherwise be a jumble of settings lay out in an easy-to-follow manner. The only real problems you will run into once
you work with these templates are cards that do not allow for enough adjustment in their settings, or cards which are lacking
in documentation. As you can imagine, you will need the documentation for each adapter card, as well as the motherboard, in
order to accurately complete a configuration table like the one shown.
TIP: Do not rely too much on software diagnostics such as MSD.EXE that claim to be able
to show hardware settings like IRQ and I/O port settings. While they can be helpful in certain situations, they are often
wrong with respect to at least some of the information they are displaying about your system. One or two items shown incorrectly
can be very troublesome if you believe the incorrect information and configure your system based on it! Unless your system
fully supports PnP, then there is simply no standard way for software to determine resource usage in a PC system. In a non-PnP
system, these programs will instead guess at how things are configured, and display these guesses with confidence, even though
they may be incorrect.
Heading Off Problems: Special Boards
A number of devices that you may want to install in a computer system require IRQ lines or DMA channels, which means that
a world of conflict could be waiting in the box that the device comes in. As mentioned in the preceding section, you can save
yourself problems if you use a system-configuration template to keep track of the way that your system is configured.
You also can save yourself trouble by carefully reading the documentation for a new adapter board before you attempt to
install it. The documentation details the IRQ lines that the board can use, as well as its DMA-channel requirements. In addition,
the documentation will detail the adapter's upper-memory needs for ROM and adapter.
The following sections describe some of the conflicts that you may encounter when you install some popular adapter boards.
Although the list of adapter boards covered in these sections is far from comprehensive, the sections serve as a guide to
installing complex hardware with minimum hassle. Included are tips on sound boards, SCSI host adapters, and network adapters.
Sound cards
Sound cards are probably the biggest single resource hog in your system. They usually use at least one IRQ, two DMA channels,
and multiple I/O port address ranges. This is because a sound card is actually several different pieces of hardware all on
one board. Most simple sound cards are similar to the Sound Blaster 16 from Creative Labs. Table 5.21 shows the default resources
used by the components on a typical Sound Blaster 16 card.
Table 5.21 Default Resources for Sound Blaster 16 Card
Device |
IRQ |
I/O Ports |
16-bit DMA |
8-bit DMA |
Audio |
5 |
220h-233h |
5 |
1 |
MIDI Port |
|
330h-331h |
|
|
FM Synthesizer |
|
388h-38Bh |
|
|
Game Port |
|
200h-207h |
|
|
As you can see, these cards use quite a few resources. If you take the time to read your sound board's documentation and
determine its communications-channel needs, compare those needs to the IRQ lines and DMA channels that already are in use
in your system, and then change the settings of the other adapters to avoid conflicts with the sound card, your installation
will go quickly and smoothly.
TIP: The greatest single piece of advice for installing a sound card is to put the sound
card in before all other cards except for video. In other words, let the sound card retain all of its default settings; never
change a resource setting to prevent a conflict. Instead, always change the settings of other adapters when a conflict with
the sound card arises. The problem here is that many educational and game programs that use sound are very poorly written
with respect to supporting alternate resource settings on sound cards. Save yourself some grief and let the sound card have
its way!
One example of a potential sound-board conflict is the combination of a Sound Blaster 16 and an Adaptec SCSI adapter. The
Sound and SCSI adapters will conflict on DMA 5 as well as on I/O ports 330-331. Rather than changing the settings of the sound
card, it is best to alter the SCSI adapter to the next available settings that will not conflict with the sound card or anything
else. The final settings were shown in the previous configuration template.
The cards in question (Sound Blaster 16 and AHA-1542CF) are not singled out here because there is something wrong with
them, but instead because they happen to be the most popular cards of their respective types, and as such will often be paired
together.
SCSI Adapter Boards
SCSI adapter boards use more resources than just about any other type of add-in device except perhaps a sound card. They
will often use resources that are in conflict with sound cards or network cards. A typical SCSI host adapter requires an IRQ
line, a DMA channel, a range of I/O port addresses, plus a 16K range of unused upper memory for its ROM and possible scratch-pad
RAM use. Fortunately, the typical SCSI adapter is also easy to reconfigure, and changing any of these settings should not
affect performance or software operation.
Before installing a SCSI adapter, be sure to read the documentation for the card, and make sure that any IRQ lines, DMA
channels, I/O ports, and upper memory that the card needs are available. If the system resources that the card needs are already
in use, use your system-configuration template to determine how you can alter the settings on the SCSI card or other cards
to prevent any resource conflicts before you attempt to plug in the adapter card.
Network Interface Cards (NICs)
A typical network adapter does not require as many resources as some of the other cards discussed here, but will require
at least a range of I/O port addresses and an interrupt. Most NICs will also require a 16K range of free upper memory to be
used for the RAM transfer buffer on the network card. As with any other cards, make sure that all of these resources are unique
to the card, and are not shared with any other devices.
Multiple-COM-Port Adapters
A serial port adapter usually has two or more ports on-board. These COM ports require an interrupt and a range of I/O ports
each. There aren't too many problems with the I/O port addresses, because the ranges used by up to four COM ports in a system
are fairly well defined. The real problem is with the interrupts. Most older installations of more than two serial ports have
any additional ones sharing the same interrupts as the first two. This is incorrect, and will cause nothing but problems with
software that runs under Windows or OS/2. With these older boards, make sure that each serial port in your system has a unique
I/O port address range, and more importantly, a unique interrupt setting.
Because the number of COM ports that can be used is strictly limited by the IRQ setup in the basic IBM system design, special
COM-port cards are available that enable you to assign a unique IRQ to each of the COM ports on the card. For example, you
can use such a card to leave COM1: and COM2: configured for IRQ 4 and IRQ 3, respectively, but to configure COM3: for IRQ
10 and COM4: for IRQ 12 (provided you do not have a motherboard-based mouse port in your system).
Many newer multiport adapter cards--such as those offered by Byte Runner Technologies--allow "intelligent" interrupt sharing
among ports. In some cases, you can have up to 12 COM port settings without conflict problems. Check with your adapter card's
manufacturer to determine if it allows for automatic or "intelligent" interrupt sharing.
Although most people have problems incorrectly trying to share interrupts when installing more than two serial ports in
a system, there is a fairly common problem with the I/O port addressing that should be mentioned. Many of the newer high-performance
SVGA (Super VGA) chipsets, such as those from S3 Inc. and ATI, use some additional I/O port addresses that will conflict with
the standard I/O port addresses used by COM4:.
In the example system-configuration just covered, you can see that the ATI video card uses some additional I/O port addresses,
specifically 2EC-2EF. This is a problem as COM4: is normally configured as 2E8-2EF, which overlaps with the video card. The
video cards that use these addresses are not normally adjustable for this setting, so you will either have to change the address
of COM4: to a nonstandard setting, or simply disable COM4: and restrict yourself to using only three serial ports in the system.
If you do have a serial adapter that supports nonstandard I/O address settings for the serial ports, you must ensure that
those settings are not used by other cards, and you must inform any software or drivers, such as those in Windows, of your
nonstandard settings.
With a multiple-COM-port adapter card installed and properly configured for your system, you can have devices hooked to
numerous COM ports, and up to four devices can be functioning at the same time. For example, you can use a mouse, modem, plotter,
and serial printer at the same time.
Plug and Play Systems
Plug and Play (PnP) represents a major revolution in the interface technology. PnP first came on the market in 1995. In
the past, PC users have been forced to muddle through a nightmare of DIP switches and jumpers every time they wanted to add
new devices to their systems. The results, all too often, were system resource conflicts and non-functioning cards.
PnP is not an entirely new concept. It was a key design feature of MCA and EISA interfaces, but the limited appeal of MCA
and EISA meant that they never became industry standards. Therefore, mainstream PC users still worry about I/O addresses,
DMA channels, and IRQ settings. But now that PnP specifications are available for ISA-, PCI-, SCSI-, IDE-, and PCMCIA-based
systems, worry-free hardware setup is within the grasp of all new computer buyers.
Of course, PnP may well be within your grasp, but that does not necessarily mean you are ready to take advantage of it.
For PnP to work, the following components are required:
- PnP hardware
- PnP BIOS
- PnP operating system (optional)
Each of these components needs to be PnP-compatible, meaning that it complies with the PnP specifications.
The Hardware Component
The hardware component refers to both computer systems and adapter cards. The term does not mean, however, that
you cannot use your older ISA adapter cards (referred to as legacy cards) in a PnP system. You can use these cards;
in fact, your PnP BIOS automatically re-assigns PnP-compatible cards around existing legacy components. PnP adapter cards
communicate with the system BIOS and the operating system to convey information about what system resources are needed. The
BIOS and operating system, in turn, resolve conflicts (wherever possible) and inform the adapter cards which specific resources
it should use. The adapter card then can modify its configuration to use the specified resources.
The BIOS Component
The BIOS component means that most users of older PCs need to update their BIOSes or purchase new machines that have PnP
BIOSes. For a BIOS to be compatible, it must support 13 additional system function calls, which can be used by the OS component
of a PnP system. The PnP BIOS specification was developed jointly by Compaq, Intel, and Phoenix Technologies. The PnP features
of the BIOS are implemented through an expanded POST. The BIOS is responsible for identification, isolation, and possible
configuration of PnP adapter cards. The BIOS accomplishes these tasks by performing the following steps:
- 1. Disable any configurable devices on the motherboard or on adapter cards.
2. Identify any PnP PCI or ISA devices.
3. Compile an initial resource-allocation map for ports, IRQs, DMAs, and memory.
4. Enable I/O devices.
5. Scan the ROMs of ISA devices.
6. Configure initial-program-load (IPL) devices, which are used later to boot the system.
7. Enable configurable devices by informing them which resources have been assigned to them.
8. Start the bootstrap loader.
9. Transfer control to the operating system.
The Operating-System Component
The operating-system component can be implemented by most newer systems, such as OS/2, Windows 95, or DOS extensions. Extensions
of this type should be familiar to most DOS users; extensions have been used for years to provide support for CD-ROM drives.
If you are using Windows NT 4.0, PnP drivers may or may not have been loaded automatically. If not, the driver can be found
on the Windows NT 4.0 CD in the DRVLIB\PNPISA\ directory. Open the correct subdirectory for your chipset and install the file
PNPISA.INF.
It is the responsibility of the operating system to inform users of conflicts that cannot be resolved by the BIOS. Depending
on the sophistication of the operating system, the user then could configure the offending cards manually (on-screen) or turn
the system off and set switches on the physical cards. When the system is restarted, the system is checked for remaining (or
new) conflicts, any of which are brought to the user's attention. Through this repetitive process, all system conflicts are
resolved.
NOTE: Windows 95 requires at least version 1.0a of the ISA PnP BIOS. If your system does
not have the most current BIOS, you can install a BIOS upgrade. With the Flash ROM used in most PnP systems, you can just
download the new BIOS image from the system vendor or manufacturer and run the supplied BIOS update program.
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